TY  - EJOU
AU  - Yeh, Chun-Hsiu 
AU  - Lin, Xian-Zhong 
AU  - Lin, Yi-Teng 
AU  - Chou, Yung-Chen 
AU  - Shen, Wei-Cheng 

TI  - FGE-YOLO: A Lightweight YOLOv8-Based Model for Printed Circuit Board Defect Detection
T2  - Computers, Materials \& Continua

PY  - 
VL  - 
IS  - 
SN  - 1546-2226

AB  - Printed circuit board (PCB) defect detection is critical for industrial quality control, where detection models must identify small and irregular defects while satisfying real-time inspection requirements. However, conventional deep learning-based detectors often require substantial computational resources, making deployment on edge devices difficult. To address this issue, FGE-YOLO is proposed as a deployment-oriented lightweight object detection model based on YOLOv8. The proposed model integrates a FasterNet-based backbone, a GhostConv-Based Neck, and an Efficient Channel Attention (ECA) mechanism. In the backbone, standard convolutions are retained in the shallow P1 and P2 stages to preserve low-level spatial details, while FasterNet-based modules are introduced in deeper stages to reduce redundant computation. In the neck, the original C2f modules are replaced with C3Ghost modules constructed from GhostConv operations to improve multi-scale feature fusion efficiency. ECA modules are further introduced to recalibrate channel-wise feature responses and enhance defect-related feature representation. Experiments were conducted on the augmented HRIPCB dataset containing six common PCB defect categories. Compared with the YOLOv8s baseline, FGE-YOLO reduces the number of parameters from 9.8M to 2.54M and decreases the computational cost from 23.4 GFLOPs to 7.1 GFLOPs. On the workstation GPU platform, the inference speed increases from 325 to 453 FPS, while mAP@0.5 remains nearly unchanged. Although mAP@0.5:0.95 decreases from 0.786 to 0.737, the proposed model provides a practical trade-off between strict localization accuracy and computational efficiency. Deployment experiments on an NVIDIA Jetson Orin Nano Super using TensorRT FP16 further demonstrate the practical feasibility of the proposed model. Under dynamic frequency scaling, FGE-YOLO reduces the TensorRT engine size from 21.8 to 7.2 MB, decreases the end-to-end latency from 18.68 to 18.08 ms, and increases throughput from 53.54 to 55.34 FPS. It also reduces the total board energy consumption per image from 0.1971 to 0.1901 J. These results indicate that FGE-YOLO is suitable for resource-constrained PCB inspection scenarios where model compactness, inference efficiency, and energy consumption are important considerations.
KW  - PCB defect detection; FGE-YOLO; lightweight detection; GhostConv-based neck; edge deployment

DO  - 10.32604/cmc.2026.087068