TY  - EJOU
AU  - Shukhratovich, Makhkamov Bakhtiyor 
AU  - Abdusalomov, Akmalbek 
AU  - Aminjanovna, Akhmedova Nodira 
AU  - Ugli, Botirov Sokhibjon Rustam 
AU  - Sevinov, Jasur 
AU  - Kutlimuratov, Alpamis 
AU  - Vafoev, Boburjon 
AU  - Ilkhamova, Yodgorkhon 
AU  - Cho, Young Im 

TI  - Efficient Cryptographic Architectures for Edge AI and Real-Time Embedded Systems
T2  - Computers, Materials \& Continua

PY  - 
VL  - 
IS  - 
SN  - 1546-2226

AB  - This paper presents field-programmable gate array (FPGA)-based engineering optimizations of the Ascon lightweight cryptographic algorithm, targeting real-time edge AI and embedded systems. The work systematically evaluates how established design strategies, such as selective round unrolling and pipelined permutation stages, scale across heterogeneous FPGA platforms. Two architectures are explored, each optimized for different design objectives, including throughput (TP), latency, and hardware efficiency. The designs are implemented on two FPGA families, Xilinx Kintex UltraScale and the 7-Series Spartan, to evaluate scalability across both high-performance and resource-constrained platforms. Experimental results show that selective round unrolling in Architecture 2 achieves the highest TP, reaching 624.57 Mb/s on UltraScale and 377.78 Mb/s on Spartan-7, while Architecture 1 provides the lowest LUT utilization, requiring as few as 1804 LUTs. Throughput-to-area ratio analysis reveals platform-dependent efficiency, with Architecture 2 performing best on UltraScale and Architecture 1 on Spartan-7. Application mapping demonstrates suitability across smart surveillance, autonomous systems, and embedded inference nodes. The results indicate that lightweight Ascon architectures can be suitable for diverse edge environments, based on their measured TP, latency, and area characteristics.
KW  - Lightweight cryptography; FPGA architectures; edge AI systems

DO  - 10.32604/cmc.2026.085065