TY  - EJOU
AU  - Abumwais, Allam 
AU  - Amirjanov, Adil 
AU  - Uyar, Kaan 
AU  - Eleyat, Mujahed 

TI  - Dual-Port Content Addressable Memory for Cache Memory Applications
T2  - Computers, Materials \& Continua

PY  - 2022
VL  - 70
IS  - 3
SN  - 1546-2226

AB  - Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.
KW  - Multicore system; content addressable memory; dual port CAM; cache controller; set-associative cache; power dissipation

DO  - 10.32604/cmc.2022.020529