@Article{cmc.2022.023934,
AUTHOR = {S. Rooban, Moru Leela, Md. Zia Ur Rahman, N. Subbulakshmi, R. Manimegalai},
TITLE = {Design of Low Power Transmission Gate Based 9T SRAM Cell},
JOURNAL = {Computers, Materials \& Continua},
VOLUME = {72},
YEAR = {2022},
NUMBER = {1},
PAGES = {1309--1321},
URL = {http://www.techscience.com/cmc/v72n1/46872},
ISSN = {1546-2226},
ABSTRACT = {Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energy-consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.},
DOI = {10.32604/cmc.2022.023934}
}