|Computers, Materials & Continua |
Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers
1VLSI Center of Excellence, GLA University, Mathura, 281406, India
2Computer Engineering Department, Research Chair of New Emerging Technologies and 5G Networks and Beyond, College of Computer and Information Sciences, King Saud University, Saudi Arabia
3Software Engineering Department, King Saud University, Riyadh, 11543, Saudi Arabia
4Al-Nahrain University, Al-Nahrain Nano-Renewable Energy Research Center, Baghdad, Iraq
5Applied College in Abqaiq, King Faisal University, Al-Ahsa, 31982, Saudi Arabia
*Corresponding Author: Reeya Agrawal. Email: firstname.lastname@example.org
Received: 22 February 2022; Accepted: 14 April 2022
Abstract: Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.
Keywords: Current differential sense amplifier (CDSA); voltage differential sense amplifier (VDSA); voltage latch sense amplifier (VLSA); current latch sense amplifier (CLSA); charge-transfer differential sense amplifier (CTDSA); new emerging technologies
Very-large-scale integrated circuit (VLSI) industries keep getting bigger, and the demand for mobile devices and battery-powered embedded systems is getting bigger and bigger all the time . It takes up 60% to 70% of the chip area. As more chips are used, the speed of microprocessors slows down. Single-chip failure rates go up and down when a million transistors are on each chip. Cache memories now use more than half of a high-performance computer's transistors, which is expected to rise . 6TSRAMC is the most common option for built-in stock because it is vital in chips like this that work well in noisy places. The design of low-power, high-performance processors, on the other hand, was given a lot of attention . At some point, speed and power made things better. SA is an essential part of all 6TSRAMC memory blocks because it responds well to high frequency. It's the same for CMOS memories and other integrated circuits . When there is more memory, the parasite space of the bit line tends to grow. In the last few years, the amount of memory that needs a lot of energy has kept going up. Cache memory is used to speed up synchronizing with a high-speed central processing unit (CPU). It is used as a CPU register because of its economic behaviour, even though it is costlier than the main memory. Cache memory is a buffer between the CPU and (random access memory) RAM, as the memory is high-speed . It has data and instructions to easily and instantly accessible to the CPU. Cache memory is of two types, i.e., 6TSRAMC and dynamic random-access memory (DRAM). 6TSRAMC reduces the average time for data access and has a holding capacity of data than DRAM.
1.1 Low Power Reduction Techniques (LPRT)
This section discusses a small introduction of low power reduction techniques, including the working of techniques in the logic circuit and the working of transistors, as shown below .
1.1.1 Low Power Reduction Dual Sleep Technique
Space requirements for this technology are cut down because each transistor is replaced by three transistors, which takes up less space . All logic circuits have a dual sleep component as standard. Schematic 1a illustrates that a specific logic circuit requires fewer transistors.
1.1.2 Low Power Reduction Sleep Transistor Technique
Low Power Reduction Sleep Transistor Technique is a well-known technique. It is also known as Power Reduction MTCMOS Technique. Schematic 1b  shows an extra sleep PMOS transistor between the VDD and the circuit pull-up network.
1.1.3 Low Power Reduction Forced Stack Technique
In the forced stack approach, instead of using a voltage supply, PM0 is utilized in the logic circuit, and instead of ground, NM0 is used, as illustrated in the Schematic 2a. Both MOS has the same input in this approach .
1.1.4 Low Power Reduction Sleep Stack Technique
Schematic 2b illustrates its structure. When both transistors are switched off simultaneously, the resulting reverse bias causes a sub-threshold reduction in leakage current. The sleepy stack approach was solved by integrating sleep and stacking methodologies .
Apart from the introduction, Section 2 covers related work in cache memory design for single-bit architecture. Section 3 describes a functional block diagram of cache memory design for single-bit architecture. Section 4 describes the proposed single bit 6TSRAMC SA architecture with its working and schematic. Section 5 describes simulated results with output waveforms and comparisons concerning the consumption of power, delay in sensing, and several transistors. Section 6 describes the summary of the paper in the form of a conclusion and future scope.
2 Literature Review
This section describes related work done in 6TSRAMC till 2022 by different authors’ papers. The conclusion arises from Tab. 1 that 6TSRAMC is the most popular in cache memory.
3 Cache Memory Design for Single Bit Architecture
They are creating a cache memory for single-bit architecture that allows for non-destructive reads and reliable writes. These two requirements collide when it comes to the size of 6TSRAMC transistors. 6TSRAMC transistor ratios must be followed for ad writing to be read successfully [31–33]. The main building blocks of the architectural blocks of ingle bit cache memory are described below. Schematic 3 shows the block diagram of cache memory design for single bit architecture.
3.1 Circuit of Write Driver (CoWD) Working and Schematic
The CoWD function of the 6TSRAMC circuit is to rapidly discharge one of the bit-lines from pre-charge levels to below the 6TSRAMC write margin. Write Enable (WE) signal activates CoWD, which uses full-swing discharge to drive the bit line from the pre-charge stage to the ground . As illustrated in Schematic 4, the order in which word line (WL) is authorized and CoWD is triggered is unimportant for the proper writing process.
3.2 Six-Transistor Static Random Access Memory (6TSRAMC) Working and Schematic
The design of 6TSRAMC is essential for the safe and robust functioning of the architecture. The 6TSRAMC must be small, stable, robust, and yield constraints—binary data storage by a 6TSRAMC portion . The word line defines modes of operation. When all transistors are removed, and cells are separated. The word line pulls high for reading and writing functions that enable access transistors (NM8 and NM9).
A typical 6TSRAMC uses two cross-connected inverters, which create a transistor lock and access . Access transistors (NM8 and NM9) allow reading and writing to the cell and provide cell isolation when the cell is not accessible, as shown in the Schematic 5.
3.3 Sense Amplifiers (SA's)
SA is a vital memory design aspect. SA's preference and configuration determine the robustness of bit-line detection, which impacts readability and power [37–39]. Sensing operation must be non-destructive, provided that 6TSRAMCs need no data to refresh circuits after sensing.
4 Proposed Single Bit 6TSRAMC SA Architecture
In this section, all the proposed architecture schematic has been shown as well as the working of all the architecture has been defined below .
4.1 Single Bit 6TSRAMC VDSA Architecture Working and Schematic
Voltage Differential Sense Amplifier (VDSA) detects the bit-line differential voltage and generates a total rail output. The circuit is depicted in Schematic 6. The BTL and BTLBAR pair create a voltage difference when WL = high. When SAEN = high, when the required differential is reached, the cross-coupled inverter enters a positive feedback loop .
The bit-line connected SA output node is set to zero, while the other output SA1 is kept raised with a lower voltage, e.g., SA2. When the sensing amplifier is turned on, NM10 and NM11 become saturated. The NM11 device has a greater VDD input voltage than the NM10, with a lower Vgs voltage. The more significant current (NM11) results in a lower output voltage on the other NM10 device, lowering Vgs and resulting in a lower current .
4.2 Single Bit 6TSRAMC CDSA Architecture Working and Schematic
The circuit architecture for a current detecting amplifier is shown in the Schematic 7. CDSA operates by directly measuring bit-cell current. It does not rely on developing a different voltage across the bit-line [43,44]. The lower bit-line can be clamped at a greater voltage in an amplifier voltage sense. As a consequence, bit-line power pre-charge can be minimized. CDSA has two components: a transmitting circuit with unit transmission characteristics and a sensing circuit that monitors the differential current. Pre-charge and assessment are two tasks of the current mode sensing amplifier [45,46].
4.3 Single Bit 6TSRAMC CTDSA Architecture Working and Schematic
The circuit diagram of a CTDSA is shown in Schematic 8. Load transfer amplification aims to increase voltage gain by utilizing load conservation across capacitive systems . A charge is transferred from high-capacity bit lines to low-capacity amplifier output nodes in the CTDSA. The minimal voltage swing of the bit-lines results in faster speeds and reduced energy usage.
4.4 Single Bit 6TSRAMC VLSA Architecture Working and Schematic
This study created the voltage latch sense amplifier (VLSA) schematics in this study in Schematic 9. The bit-lines are used to pre-charge the internal nodes of this architecture. The circuit design employs the input bit-lines based on internal nodes [48,49].
When the word line is pushed high and before the sense amplifier signal, NM12 is turned off, and PM8 and PM9 pass transistors are turned on. The random bit on the internal nodes of the sense amplifier has an appropriate voltage difference as the differential on the bit lines grows. A differential voltage is amplified to its maximum swing output when the SAEN sensing amplifier signal is asserted [50,51].
4.5 Single Bit 6TSRAMC CLSA Architecture Working and Schematic
One of the bit lines releases throughout the reading operation, while the other remains at supply voltage. Due to the capabilities of a big bit-line, the slow discharge is moderate, and the bit cells have access to the transistor [52–54].
SA does this by amplifying a slight change in the bit line voltages at digital levels. CLSA schematic is shown in Schematic 10. The differential voltage is carried via bit-lines to the CLSA inputs SA3 and SA4. If SA1 and SA2 begin to discharge at high levels, SAEN is pulled high [55–58].
5 Simulation Results
The power consumption of all the circuits has been analyzed in this section. Tabs. 2 and 3 describe a single bit 6TSRAMC SA architecture with different parameters using different types of SA's such as (VDSA, CDSA, CTDSA, VLSA, and CLSA) at additional values of resistance (such as 42.3 Ω and 42.3 kΩ) with other parameters such as delay in sensing, several transistors and consumption of power.
From Tabs. 2 and 3, conclusions arise that singe bit 6TSRAMC VDSA architecture consumes 11.34 μW of power, the lowest among all the architectures. Due to this reason, LPRT has been applied over a single bit 6TSRAMC VDSA architecture, but there is an increment in the number of the transistor.
Tab. 4 describes different parameters of single bit 6TSRAMC VDSA architecture, and to optimize the consumption of power, techniques of power reduction are applied over VDSA. Tab. 5 describes that using LPRT over 6TSRAMC in single bit 6TSRAMC VDSA architecture also reduces the consumption of power. Due to this, there is an increment in the number of transistors in the design.
From Tabs. 4 and 5, conclusions arise that Singe Bit 6TSRAMC with LPRFST VDSA with LPRDST consumes 8.078 μW of power, which is the lowest compared to others. Schematic 11 shows the proposed schematic of single bit 6TSRAMC with LPRFST VDSA with LPRDST architecture schematic.
Schematic 12 shows the output waveform of CoWD, where WE and Data are inputs, and BTL and BTLBAR are output are described in four cases.
Case (a): WE and Data both are low, BTL and BTLBAR both are high, while,
Case (b): WE are high, Data is low, BTL is low, and BTLBAR is high,
Case (c): Data is high, and WE are low, BTL and BTLBAR are high/2,
Case (d): Data is high, WE are high, BTL is high, and BTLBAR is low.
Schematic 13 shows the output waveform of 6TSRAMC, which shows the write operation and hold operation held in the 6TSRAMC. Schematic 14 shows the output waveform of single bit 6TSRAMC VDSA architecture, i.e., reading operation done by a SA that reads the store data in 6TSRAMC. Tab. 6 describes applying LPRT over different blocks of cache memory design for single bit architecture (such as 6TSRAMC and VDSA) to optimize power consumption. Results depicted that single bit 6TSRAMC with LPRFST VDSA with LPRDST architecture consumes 8.078 μW of power which is the lowest as compared to architecture. But due to this, there is an increment in the number of transistors.
6 Conclusion and Future Scope
In this paper, cache memory design for single-bit architecture with different sense amplifiers has been implemented and analyzed. Single Bit 6TSRAMC SA Architecture comprises CoWD, 6TSRAMC, and SA (VDSA, CDSA, CTDSA, VLSA, and CLSA). All architectures are compared on different values of resistance (R) with other parameters such as consumption of power, delay in sensing and number of transistors. Results showed that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power. Furthermore, LPRT is applied over different cache memory architecture blocks to optimize power. The single-bit 6TSRAMC with LPRFST and VDSA with LPRDST consume 8.078 μW of power, i.e., reduce 28% more ability and make it more efficient.
Future Scope–This work can be done in the form of the array, and LPRT can be applied to other architectures. Moreover, other sense amplifiers can be used in architecture to reduce the drawbacks of the proposed architecture; Apart from it, these architectures can be compared over different parameters such as read delay, write delay, signal to noise margin etc.
Author Contributions: A short paragraph specifying their contributions must be provided for research articles with several authors. The following statements should be used “Conceptualization, Reeya Agrawal; methodology, Reeya Agrawal; software, cadence tool; validation, Reeya Agrawal, Anjan Kumar Salman; formal analysis, Reeya Agrawal; investigation, Reeya Agrawal; resources, Reeya Agrawal; data curation, Reeya Agrawal; writing—original draft preparation, Reeya Agrawal; writing—review and editing, Anjan Kumar; visualization, Osamah Ibrahim Khalif; supervision, Salman; project administration. All authors have read and agreed to the published version of the manuscript.
Acknowledgement: Authors are grateful to the Deanship of Scientific Research at King Saud University for funding this work through the Vice Deanship of Scientific Research Chairs: Research Chair of New Emerging Technologies 5G Networks and Beyond.
Funding Statement: Research General Direction funded this research at Universidad Santiago de Cali, Grant Number 01-2021 and APC was funded by 01-2021.
Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the present study.
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