@Article{cmc.2026.081338,
AUTHOR = {Gen Xu, Li Lv, Jiayan Dong},
TITLE = {Supporting Memory Safety with a Security-Enhanced Memory Controller},
JOURNAL = {Computers, Materials \& Continua},
VOLUME = {89},
YEAR = {2026},
NUMBER = {1},
PAGES = {--},
URL = {http://www.techscience.com/cmc/v89n1/68374},
ISSN = {1546-2226},
ABSTRACT = {Memory-unsafe languages such as C and C++ remain widely used because they provide low-level control and high performance, but they remain vulnerable to spatial and temporal memory-safety violations such as out-of-bounds accesses, buffer overflows, and use-after-free errors. Prior hardware-assisted defenses reduce software overhead, yet many still rely on CPU-side metadata checks that add latency to the critical path and often miss DMA-originated accesses. We show that metadata-access cost is not dominated solely by DRAM latency: a substantial portion of the delay comes from on-chip traversal and cache-related processing. Motivated by this result, we propose SerMC, a memory-controller-based tripwire mechanism that validates accesses when metadata arrives from Dynamic Random Access Memory (DRAM) and extends enforcement to DRAM-bound accesses issued by both processors and DMA-capable devices. SerMC keeps metadata checks off the CPU critical path while preserving compatibility with existing C/C++ programs. The design targets spatial and temporal violations that cross tripwire-protected DRAM regions; non-linear pointer corruption that avoids such regions and microarchitectural side channels remain outside the scope of the current design. Our evaluation on selected SPEC CPU workloads shows 9.25% average performance overhead, while the most memory-intensive workloads incur slowdowns of up to 50%. These results indicate that SerMC provides practical average-case overhead but still exposes a clear worst-case tradeoff when metadata traffic competes with demand memory requests.},
DOI = {10.32604/cmc.2026.081338}
}