TY  - EJOU
AU  - Xu, Gen 
AU  - Lv, Li 
AU  - Dong, Jiayan 

TI  - Supporting Memory Safety with a Security-Enhanced Memory Controller
T2  - Computers, Materials \& Continua

PY  - 2026
VL  - 89
IS  - 1
SN  - 1546-2226

AB  - Memory-unsafe languages such as C and C++ remain widely used because they provide low-level control and high performance, but they remain vulnerable to spatial and temporal memory-safety violations such as out-of-bounds accesses, buffer overflows, and use-after-free errors. Prior hardware-assisted defenses reduce software overhead, yet many still rely on CPU-side metadata checks that add latency to the critical path and often miss DMA-originated accesses. We show that metadata-access cost is not dominated solely by DRAM latency: a substantial portion of the delay comes from on-chip traversal and cache-related processing. Motivated by this result, we propose SerMC, a memory-controller-based tripwire mechanism that validates accesses when metadata arrives from Dynamic Random Access Memory (DRAM) and extends enforcement to DRAM-bound accesses issued by both processors and DMA-capable devices. SerMC keeps metadata checks off the CPU critical path while preserving compatibility with existing C/C++ programs. The design targets spatial and temporal violations that cross tripwire-protected DRAM regions; non-linear pointer corruption that avoids such regions and microarchitectural side channels remain outside the scope of the current design. Our evaluation on selected SPEC CPU workloads shows 9.25% average performance overhead, while the most memory-intensive workloads incur slowdowns of up to 50%. These results indicate that SerMC provides practical average-case overhead but still exposes a clear worst-case tradeoff when metadata traffic competes with demand memory requests.
KW  - Memory safety; cyber security; memory vulnerability exploitation; tripwire-based defense

DO  - 10.32604/cmc.2026.081338