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Timing Error Aware Register Allocation in TS

Sheng Xiao1,2,*, Jing He3, Xi Yang4, Heng Zhou1, Yujie Yuan1

1 Information Science and Engineering Department, Hunan First Normal University, Changsha, 410205, China
2 Computer School, Wuhan University, Wuhan, 430072, China
3 Department of Computer Science, Kennesaw State University, Kennesaw, 30144-5588, USA
4 Hunan Guangyi Experimental Middle School, Changsha, 410205, China

* Corresponding Author: Sheng Xiao. Email: email

TSP_CSSE_19106.pdf

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