TY  - EJOU
AU  - Jain, Arpit 
AU  - Kumar, Adesh 
AU  - Shukla, Anand Prakash 
AU  - Alshazly, Hammam 
AU  - Elmannai, Hela 
AU  - Algarni, Abeer D. 
AU  - Kumar, Roushan 
AU  - Yadav, Jitendra 

TI  - Smart Communication Using 2D and 3D Mesh Network-on-Chip
T2  - Intelligent Automation \& Soft Computing

PY  - 2022
VL  - 34
IS  - 3
SN  - 2326-005X

AB  - Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D and 3D mesh NoC respectively. The functional simulation is performed on Modelsim 10.0 software. The on-chip communicationis verified for 2D and 3D mesh NoC with different cluster sizes that pre-estimates the hardware resources utilization on FPGA. The algorithm provides a substantial platform to NoC designers to overcome the issues of substantial configuration in NoC synthesis on FPGA in case of multiple processing elements, routers, cache controllers are integrated with SoC. The suggested NoC is helpful for the embedded system design of smart wireless communication.
KW  - Smart communication; NoC; SoC; file programmeble gate array

DO  - 10.32604/iasc.2022.024770