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  • Open Access


    Medical Image Demosaicing Based Design of Newton Gregory Interpolation Algorithm

    E. P. Kannan1,*, S. S. Vinsley2, T. V. Chithra3

    Intelligent Automation & Soft Computing, Vol.34, No.3, pp. 1675-1691, 2022, DOI:10.32604/iasc.2022.022707

    Abstract In this paper, Field-Programmable Gate Array (FPGA) implementation-based image demosaicing is carried out. The Newton Gregory interpolation algorithm is designed based on FPGA frame work. Interpolation is the method of assessing the value of a function for any in-between value of self-regulating variable, whereas the method of computing the value of the function outside the specified range is named extrapolation. The natural images are collected from Kodak image database and medical images are collected from UPOL (University of Phoenix Online) database. The proposed algorithm is executed on using Xilinx ISE (Integrated Synthesis Environment) Design Suite 14.2 and is confirmed on… More >

  • Open Access


    FPGA Implementation of Elliptic-Curve Diffie Hellman Protocol

    Sikandar Zulqarnain Khan1,*, Sajjad Shaukat Jamal2, Asher Sajid3, Muhammad Rashid4

    CMC-Computers, Materials & Continua, Vol.73, No.1, pp. 1879-1894, 2022, DOI:10.32604/cmc.2022.028152

    Abstract This paper presents an efficient crypto processor architecture for key agreement using ECDH (Elliptic-curve Diffie Hellman) protocol over . The composition of our key-agreement architecture is expressed in consisting of the following: (i) Elliptic-curve Point Multiplication architecture for public key generation (DESIGN-I) and (ii) integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation (DESIGN-II). The arithmetic operators used in DESIGN-I and DESIGN-II contain an adder, squarer, a multiplier and inversion. A simple shift and add multiplication method is employed to retain lower hardware resources. Moreover, an essential inversion operation is operated using the Itoh-Tsujii… More >

  • Open Access


    FPGA Implementation of 5G NR Primary and Secondary Synchronization

    Aytha Ramesh Kumar1,*, K. Lal Kishore2

    CMC-Computers, Materials & Continua, Vol.73, No.1, pp. 1585-1600, 2022, DOI:10.32604/cmc.2022.021573

    Abstract The 5G communication systems are widely established for high-speed data processing to meet users demands. The 5G New Radio (NR) communications comprise a network of ultra-low latency, high processing speeds, high throughput and rapid synchronization with a time frame of 10 ms. Synchronization between User Equipment (UE) and 5G base station known as gNB is a fundamental procedure in a cellular system and it is performed by a synchronization signal. In 5G NR system, Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS) are used to detect the best serving base station with the help of a cell search procedure.… More >

  • Open Access


    Field Programmable Gate Arrays (FPGA) Based Computational Complexity Analysis of Multicarrier Waveforms

    C. Ajitha1,*, T. Jaya2

    Intelligent Automation & Soft Computing, Vol.34, No.2, pp. 1033-1048, 2022, DOI:10.32604/iasc.2022.021984

    Abstract Multicarrier waveforms with enhanced spectral efficiency, low latency, and high throughput are required for 5G wireless networks. The Orthogonal Frequency Division Multiplexing (OFDM) method is well-known in research, but due to its limited spectral efficiency, various alternative waveforms are being considered for 5G systems. In the recent communication world, NOMA (non-orthogonal multiple access) plays a significant part due to its wider transmission of data with less bandwidth allocation. Even if a high data rate can be attained, the transmission problem will arise due to the spread of multiple paths. In order to reduce complexity and area utilization, a novel PL-based… More >

  • Open Access


    An FPGA Design for Real-Time Image Denoising

    Ahmed Ben Atitallah*

    Computer Systems Science and Engineering, Vol.43, No.2, pp. 803-816, 2022, DOI:10.32604/csse.2022.024393

    Abstract The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is… More >

  • Open Access


    Smart Grid Security by Embedding S-Box Advanced Encryption Standard

    Niraj Kumar1,*, Vishnu Mohan Mishra2, Adesh Kumar3

    Intelligent Automation & Soft Computing, Vol.34, No.1, pp. 623-638, 2022, DOI:10.32604/iasc.2022.024804

    Abstract Supervisory control and data acquisition (SCADA) systems continuously monitor the real-time processes in the smart grid. The system software, which is based on a human-machine interface (HMI), makes intelligent decisions to assist the system operator and perform normal grid management activities. The management of SCADA networks and monitoring without proper security is a major concern, as many grids and plant networks still lack necessary monitoring and detection systems, making them vulnerable to attack. SCADA networks exploit physical weaknesses as well as cyber-attacks. Researchers have developed a monitoring system based on a field-programmable gate array (FPGA) and a microcontroller that allows… More >

  • Open Access


    A Resource-Efficient Convolutional Neural Network Accelerator Using Fine-Grained Logarithmic Quantization

    Hadee Madadum*, Yasar Becerikli

    Intelligent Automation & Soft Computing, Vol.33, No.2, pp. 681-695, 2022, DOI:10.32604/iasc.2022.023831

    Abstract Convolutional Neural Network (ConNN) implementations on Field Programmable Gate Array (FPGA) are being studied since the computational capabilities of FPGA have been improved recently. Model compression is required to enable ConNN deployment on resource-constrained FPGA devices. Logarithmic quantization is one of the efficient compression methods that can compress a model to very low bit-width without significant deterioration in performance. It is also hardware-friendly by using bitwise operations for multiplication. However, the logarithmic suffers from low resolution at high inputs due to exponential properties. Therefore, we propose a modified logarithmic quantization method with a fine resolution to compress a neural network… More >

  • Open Access


    An Efficient HW/SW Design for Text Extraction from Complex Color Image

    Mohamed Amin Ben Atitallah1,2,3,*, Rostom Kachouri2, Ahmed Ben Atitallah4, Hassene Mnif1

    CMC-Computers, Materials & Continua, Vol.71, No.3, pp. 5963-5977, 2022, DOI:10.32604/cmc.2022.024345

    Abstract In the context of constructing an embedded system to help visually impaired people to interpret text, in this paper, an efficient High-level synthesis (HLS) Hardware/Software (HW/SW) design for text extraction using the Gamma Correction Method (GCM) is proposed. Indeed, the GCM is a common method used to extract text from a complex color image and video. The purpose of this work is to study the complexity of the GCM method on Xilinx ZCU102 FPGA board and to propose a HW implementation as Intellectual Property (IP) block of the critical blocks in this method using HLS flow with taking account the… More >

  • Open Access


    Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

    Turki M. Alanazi, Ahmed Ben Atitallah*

    CMC-Computers, Materials & Continua, Vol.71, No.3, pp. 4319-4335, 2022, DOI:10.32604/cmc.2022.022988

    Abstract As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for… More >

  • Open Access


    Light-Weight Present Block Cipher Model for IoT Security on FPGA

    R. Bharathi*, N. Parvatham

    Intelligent Automation & Soft Computing, Vol.33, No.1, pp. 35-49, 2022, DOI:10.32604/iasc.2022.020681

    Abstract The Internet of Things (IoT) plays an essential role in connecting a small number of billion devices with people for diverse applications. The security and privacy with authentication are challenging work for IoT devices. A light-weight block cipher is designed and modeled with IoT security for real-time scenarios to overcome the above challenges. The light-weight PRESENT module with the integration of encryption (E)-decryption (D) is modeled and implemented on FPGA. The PRESENT module has 64-bit data input with 80/128/256-bit symmetric keys for IoT security. The PRESENT module performs16/32/64 round operations for state register and key updation. The design mainly uses… More >

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