Hadee Madadum^*, Yasar Becerikli

Intelligent Automation & Soft Computing, Vol.33, No.2, pp. 681-695, 2022, DOI:10.32604/iasc.2022.023831 - 08 February 2022

Abstract Convolutional Neural Network (ConNN) implementations on Field Programmable Gate Array (FPGA) are being studied since the computational capabilities of FPGA have been improved recently. Model compression is required to enable ConNN deployment on resource-constrained FPGA devices. Logarithmic quantization is one of the efficient compression methods that can compress a model to very low bit-width without significant deterioration in performance. It is also hardware-friendly by using bitwise operations for multiplication. However, the logarithmic suffers from low resolution at high inputs due to exponential properties. Therefore, we propose a modified logarithmic quantization method with a fine resolution More >

Mohamed Amin Ben Atitallah^1,2,3,*, Rostom Kachouri², Ahmed Ben Atitallah⁴, Hassene Mnif¹

CMC-Computers, Materials & Continua, Vol.71, No.3, pp. 5963-5977, 2022, DOI:10.32604/cmc.2022.024345 - 14 January 2022

Abstract In the context of constructing an embedded system to help visually impaired people to interpret text, in this paper, an efficient High-level synthesis (HLS) Hardware/Software (HW/SW) design for text extraction using the Gamma Correction Method (GCM) is proposed. Indeed, the GCM is a common method used to extract text from a complex color image and video. The purpose of this work is to study the complexity of the GCM method on Xilinx ZCU102 FPGA board and to propose a HW implementation as Intellectual Property (IP) block of the critical blocks in this method using HLS More >

Turki M. Alanazi, Ahmed Ben Atitallah^*

CMC-Computers, Materials & Continua, Vol.71, No.3, pp. 4319-4335, 2022, DOI:10.32604/cmc.2022.022988 - 14 January 2022

Abstract As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement… More >

R. Bharathi^*, N. Parvatham

Intelligent Automation & Soft Computing, Vol.33, No.1, pp. 35-49, 2022, DOI:10.32604/iasc.2022.020681 - 05 January 2022

Abstract The Internet of Things (IoT) plays an essential role in connecting a small number of billion devices with people for diverse applications. The security and privacy with authentication are challenging work for IoT devices. A light-weight block cipher is designed and modeled with IoT security for real-time scenarios to overcome the above challenges. The light-weight PRESENT module with the integration of encryption (E)-decryption (D) is modeled and implemented on FPGA. The PRESENT module has 64-bit data input with 80/128/256-bit symmetric keys for IoT security. The PRESENT module performs16/32/64 round operations for state register and key… More >

Arpit Jain¹, Rakesh Kumar Dwivedi¹, Hammam Alshazly^2,*, Adesh Kumar³, Sami Bourouis⁴, Manjit Kaur⁵

CMC-Computers, Materials & Continua, Vol.71, No.2, pp. 4085-4100, 2022, DOI:10.32604/cmc.2022.023017 - 07 December 2021

Abstract The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect… More >

P. N. Palanisamy^*, N. Malmurugan

CMC-Computers, Materials & Continua, Vol.71, No.1, pp. 791-808, 2022, DOI:10.32604/cmc.2022.019921 - 03 November 2021

Abstract In recent years, deep neural networks have become a fascinating and influential research subject, and they play a critical role in video processing and analytics. Since, video analytics are predominantly hardware centric, exploration of implementing the deep neural networks in the hardware needs its brighter light of research. However, the computational complexity and resource constraints of deep neural networks are increasing exponentially by time. Convolutional neural networks are one of the most popular deep learning architecture especially for image classification and video analytics. But these algorithms need an efficient implement strategy for incorporating more real… More >

Namit Gupta^1,*, Kunwar Singh Vaisla², Arpit Jain³, Adesh Kumar⁴, Rajeev Kumar³

Computer Systems Science and Engineering, Vol.40, No.3, pp. 1073-1084, 2022, DOI:10.32604/csse.2022.019911 - 24 September 2021

Abstract Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. More >

T. Manoj Kumar^1,*, P. Karthigaikumar²

Intelligent Automation & Soft Computing, Vol.31, No.2, pp. 1025-1036, 2022, DOI:10.32604/iasc.2022.020090 - 22 September 2021

Abstract

Data security is an essential aspect of data communication and data storage. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. Several modifications have been made to the original architecture after it was proposed by two Belgian researchers, Joan Daemen and Vincent Rijment, at the third AES candidate Conference in 2000. The existing modifications aim to increase security and speed.

… More >

Amit Kumar¹, Adesh Kumar^2,*, Geetam Singh Tomar³

Computer Systems Science and Engineering, Vol.40, No.2, pp. 645-659, 2022, DOI:10.32604/csse.2022.019449 - 09 September 2021

Abstract The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter… More >

Praveenkumar Babu, Eswaran Parthasarathy^*

Intelligent Automation & Soft Computing, Vol.30, No.3, pp. 1063-1071, 2021, DOI:10.32604/iasc.2021.018903 - 20 August 2021

Abstract Advancements in image and video processing are growing over the years for industrial robots, autonomous vehicles, indexing databases, surveillance, medical imaging and computer-human interaction applications. One of the major challenges in real-time image and video processing is the execution of complex functions and high computational tasks. In this paper, the hardware acceleration of different filter algorithms for both image and video processing is implemented on Xilinx Zynq^®-7000 System on-Chip (SoC) device. It consists of Dual-core Cortex^™-A9 processors which provide computing ability to perform I/O and processing functions and software libraries using Vivado^® High-Level Synthesis (HLS). In the More >