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  • Open Access

    ARTICLE

    Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

    Turki M. Alanazi, Ahmed Ben Atitallah*

    CMC-Computers, Materials & Continua, Vol.71, No.3, pp. 4319-4335, 2022, DOI:10.32604/cmc.2022.022988

    Abstract As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for… More >

  • Open Access

    ARTICLE

    Light-Weight Present Block Cipher Model for IoT Security on FPGA

    R. Bharathi*, N. Parvatham

    Intelligent Automation & Soft Computing, Vol.33, No.1, pp. 35-49, 2022, DOI:10.32604/iasc.2022.020681

    Abstract The Internet of Things (IoT) plays an essential role in connecting a small number of billion devices with people for diverse applications. The security and privacy with authentication are challenging work for IoT devices. A light-weight block cipher is designed and modeled with IoT security for real-time scenarios to overcome the above challenges. The light-weight PRESENT module with the integration of encryption (E)-decryption (D) is modeled and implemented on FPGA. The PRESENT module has 64-bit data input with 80/128/256-bit symmetric keys for IoT security. The PRESENT module performs16/32/64 round operations for state register and key updation. The design mainly uses… More >

  • Open Access

    ARTICLE

    Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

    Arpit Jain1, Rakesh Kumar Dwivedi1, Hammam Alshazly2,*, Adesh Kumar3, Sami Bourouis4, Manjit Kaur5

    CMC-Computers, Materials & Continua, Vol.71, No.2, pp. 4085-4100, 2022, DOI:10.32604/cmc.2022.023017

    Abstract The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher… More >

  • Open Access

    ARTICLE

    FPGA Implementation of Deep Leaning Model for Video Analytics

    P. N. Palanisamy*, N. Malmurugan

    CMC-Computers, Materials & Continua, Vol.71, No.1, pp. 791-808, 2022, DOI:10.32604/cmc.2022.019921

    Abstract In recent years, deep neural networks have become a fascinating and influential research subject, and they play a critical role in video processing and analytics. Since, video analytics are predominantly hardware centric, exploration of implementing the deep neural networks in the hardware needs its brighter light of research. However, the computational complexity and resource constraints of deep neural networks are increasing exponentially by time. Convolutional neural networks are one of the most popular deep learning architecture especially for image classification and video analytics. But these algorithms need an efficient implement strategy for incorporating more real time computations in terms of… More >

  • Open Access

    ARTICLE

    Performance Analysis of AODV Routing for Wireless Sensor Network in FPGA Hardware

    Namit Gupta1,*, Kunwar Singh Vaisla2, Arpit Jain3, Adesh Kumar4, Rajeev Kumar3

    Computer Systems Science and Engineering, Vol.40, No.3, pp. 1073-1084, 2022, DOI:10.32604/csse.2022.019911

    Abstract Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip… More >

  • Open Access

    ARTICLE

    Implementation of a High-Speed and High-Throughput Advanced Encryption Standard

    T. Manoj Kumar1,*, P. Karthigaikumar2

    Intelligent Automation & Soft Computing, Vol.31, No.2, pp. 1025-1036, 2022, DOI:10.32604/iasc.2022.020090

    Abstract

    Data security is an essential aspect of data communication and data storage. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. Several modifications have been made to the original architecture after it was proposed by two Belgian researchers, Joan Daemen and Vincent Rijment, at the third AES candidate Conference in 2000. The existing modifications aim to increase security and speed. This paper proposes an efficient… More >

  • Open Access

    ARTICLE

    Hardware Chip Performance of CORDIC Based OFDM Transceiver for Wireless Communication

    Amit Kumar1, Adesh Kumar2,*, Geetam Singh Tomar3

    Computer Systems Science and Engineering, Vol.40, No.2, pp. 645-659, 2022, DOI:10.32604/csse.2022.019449

    Abstract The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver respectively. The coordinate… More >

  • Open Access

    ARTICLE

    Hardware Acceleration of Image and Video Processing on Xilinx Zynq Platform

    Praveenkumar Babu, Eswaran Parthasarathy*

    Intelligent Automation & Soft Computing, Vol.30, No.3, pp. 1063-1071, 2021, DOI:10.32604/iasc.2021.018903

    Abstract Advancements in image and video processing are growing over the years for industrial robots, autonomous vehicles, indexing databases, surveillance, medical imaging and computer-human interaction applications. One of the major challenges in real-time image and video processing is the execution of complex functions and high computational tasks. In this paper, the hardware acceleration of different filter algorithms for both image and video processing is implemented on Xilinx Zynq®-7000 System on-Chip (SoC) device. It consists of Dual-core Cortex-A9 processors which provide computing ability to perform I/O and processing functions and software libraries using Vivado® High-Level Synthesis (HLS). In the proposed work, Sobel-Feldman… More >

  • Open Access

    ARTICLE

    PSO Based Torque Ripple Minimization Of Switched Reluctance Motor Using FPGA Controller

    A. Manjula1,*, L. Kalaivani2, M. Gengaraj2

    Intelligent Automation & Soft Computing, Vol.29, No.2, pp. 451-465, 2021, DOI:10.32604/iasc.2021.016088

    Abstract The fast-growing field of mechanical robotization necessitates a well-designed and controlled version of electric drives. The concept of control concerning mechanical characteristics also requires a methodology in which the system needs to be modeled precisely and deals with uncertainty. The proposed method provides the enhanced performance of Switched Reluctance Motor (SRM) by controlling its speed and minimized torque ripple. Proportional-Integral-Derivative (PID) controllers have drawn more attention in industry automation due to their ease and robustness. The performances are further improved by using fractional order (Non-integer) controllers. The Modified Particle Swarm Optimization (MPSO) based optimization approach is employed to acquire the… More >

  • Open Access

    ARTICLE

    An Optimized SW/HW AVMF Design Based on High-Level Synthesis Flow for Color Images

    Turki M. Alanazi1, Ahmed Ben Atitallah1,2,*, Imen Abid2

    CMC-Computers, Materials & Continua, Vol.68, No.3, pp. 2925-2943, 2021, DOI:10.32604/cmc.2021.017575

    Abstract In this paper, a software/hardware High-level Synthesis (HLS) design is proposed to compute the Adaptive Vector Median Filter (AVMF) in real-time. In fact, this filter is known by its excellent impulsive noise suppression and chromaticity conservation. The software (SW) study of this filter demonstrates that its implementation is too complex. The purpose of this work is to study the impact of using an HLS tool to design ideal floating-point and optimized fixed-point hardware (HW) architectures for the AVMF filter using square root function (ideal HW) and ROM memory (optimized HW), respectively, to select the best HLS architectures and to design… More >

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