Performance Enhancement of PV Based Boost Cascaded Fifteen Level Inverter for AC Loads

In this research work, single-stage fifteen levels cascaded DC-interface converter (CDDCLC) is proposed for sun arranged photovoltaic technology (PV) applications. The proposed geography is joined with help DC chopper and H-associate inverter to upgrade the power converter to accomplish the diminished harmonic profile. In assessment with the customary inverter structures, the proposed system is used with diminished voltage stress, decreased switch count and DC source tally. The proposed research work with cascaded DC link converter design requires three DC sources for combining fifteen-level AC output. This investigation structure switching technique is phase opposition and disposition pulse width modulation technique (POPD) which results in improved quality of obtained output AC power with 6.73% THD and also determinedly recommended for power converters used in UPS and drive applications since it is extremely affordable. A simulation and prototype model of fifteen-level CDDCLC system is deployed and its performance is analyzed for various operating conditions.


Introduction
The new type of power converter options for high-power functions appear in multilevel inverters (MLIs) in power converters, particularly for sustainable power source combinations and uninterruptible power supplies [1,2]. MLI's traditional multilevel inverter topologies are flying capacitor MLI (FCMLI), diode clamped MLI and cascaded multilevel inverter CMLI [3,4]. Each topology has its advantages and limitations. CMLI synthesizes the AC voltage waveform of the staircase from a few DC sources among the setup with decreased consonant substance [5]. So the configuration of CMLI is more desirable than the other two configurations.
In order to achieve the nominal output voltage in CMLI, [6,7], a step-up dc-dc converter is connected between DC sources and H-bridges. In view of the quantity of regulated force switches and DC sources, the feasibility of the CMLI and lift CMLI (BCMLI) configurations [8] is compromised.
Some modifications can be made in the standard CMLI and BCMLI frameworks [9][10][11][12] in this process. CMLI with decreased switch count is proposed in this framework. In addition, it is shown that the ostensible yield voltage is obtained by presenting the raise chopper circuit between the DC sources and the DC-interface inverter.
The Boost Chopper Network raises the DC input voltage to the nominal voltage level. This results in the number of DC sources and power switches being decreased. In this paper, for UPS applications, a singlephase fifteen-level asymmetrical source boost DC-link CMLI (BDCLCMLI) system is developed. For DC-link switches [13][14][15][16][17][18][19][20][21], a multicarrier sinusoidal pulse-width modulation (MCSPWM) switching strategy has been developed to obtain a better quality of AC power with an improved harmonic profile.
For each H-bridge and m-level inverter, a separate DC bus is needed; 2 (m−1) numbers of switches per step and 2 (m−1) numbers of ant parallel diodes are required. Topology of seven level cascaded multilevel inverter with RL load is shown in Fig. 1.
A single-phase seven-level asymmetrical source boost converter in deployed in this work. [Uthirasamy et al. (2014)]. The BDCLCMLI (DC-link CMLI) framework is optimized for UPS Applications. The general structure of the BDCLCMLI seven level scheme is shown in Fig. 2. For DC-link switches, multicarrier sinusoidal pulse-width modulation (MCSPWM) switching strategy is built to obtain better quality of AC power (with reduced harmonic content). Circuit diagram of fifteen levels Boost DC-link which is cascaded with multilevel inverter is given in Fig. 3.
The dc/dc converter extricates the greatest power from the dc-interface to the PV series. [Ajami et al. (2013)]. It should be noted that the immediate association of the PV string to the dc-connect, due to the second consonant swaying of the dc-interface, results in a wavering of the PV string's extricated power.

Configuration of BDCLCMLI System
Three lopsided DC voltage sources, support chopper unit, DC-connect module (DCLM) and a typical H-connect inverter establish a BDCLCMLI framework. Further, in corresponding to the DC-interface framework H-connect inverter is associated. The BDCLCMLI configuration withholds various numbers of levels and switches which is calculated by Eqs. (1) and (2), where,  The proposed topology consists of two parts, they are i. Boost chopper with Solar input ii. Level generation unit with Common H bridge

Boost Chopper with Solar Input
The asymmetrical DC source output voltage is always unidirectional. And each boost chopper unit is connected with asymmetrical DC sources.

Level Generation Unit with Common H Bridge
The proposed asymmetrical multilevel inverter is made up of two parts. They are the Level generation unit and common H Bridge. The boost chopper output voltage of isolated sources is switched via the level generation unit to produce the desired fifteen levels. The switching states are listed in Tab. 1. The asymmetrical topology produces fifteen levels when compared to the symmetrical one whereas the conventional topology produces only seven levels. Hence the topology saves the number of switches and sources.
The level generation unit having sub-modules can produce only unidirectional voltage. So a common H bridge is used to reverse the generated voltage. This in turn helps to produce bipolar symmetrical waveform and reduces the individual H bridge at the same time. The switches in the level generation unit are marked as T1, T2 and T3. The common H bridges marked as H1, H2, H3 and H4.

Operating Modes
The proposed system is switched under nine states to obtain fifteen-level. The ac output voltage level is controlled through multi carrier PWM. The operation of level generation unit is explained from Mode 1 to Mode 8 as shown in Figs. 5a-5h. The reverse voltage technique is explained through Mode 9 in Fig. 5i.
The lift chopper switch S b is turned ON at t = T ON2 and current which flows through inductor L2 varies linearly from I 3 to I 4 Hence, the voltage across inductor L2 is derived as Now, vitality contribution to inductor L2 from the source At t = T OFF2 the lift chopper switch S b is switched OFF and current through the inductor L 2 flows linearly from I 4 to I 3.
Average output voltage of boost chopper II is obtained During this time, the energy which is released by the inductor L 2 to B DCIM is given by, The change in voltage over the capacitor C2 is derived by Voltage across the inductor 4 is derived as The vitality contribution to inductor 4 from source Vd1 is identified as At t = T OFF1 lift chopper switch Sa is switched OFF and the current which flows through inductor 4 falls linearly from I 2 to I 1 .
At t = T OFF1 lift chopper switch Sa is switched OFF and the current through the inductor 4 falls linearly from I 2 to I 1 The normal yield voltage of lift chopper I can be expressed as At this moment the energy which is released by inductor L1 to the BDCLM is given by The ripple in the inductor current can be obtained as The adjustment in voltage overCapacitor t1 can be written as At t = TON3 boost chopper switch S a and S b are turned ON and current through the inductors L 1 and L 2 increases gradually from I 1 to I 2 and I 3 to I 4 respectively.
At right now, vitality contribution to inductor L 1 from source V d1 and energy fed to the inductor L 2 from source Vd 2 are Boost chopper switches S a and S b are switched OFF and current through inductor L 1 and L 2 drops linearly from I 2 to I 1 and from I 4 to I 3 .
At this moment the energy discharged from inductor L 1 and L 2 to B DCLM is given by, The adjustment in voltageacross capacitor C 1 and C 2 is expressed as The positive half cycle magnitude of AC output voltage are written as The negative half cycle magnitude of AC output voltage are expressed as To produce positive or negative seven levels, the switches T1-T3 are operated as per the switching pattern listed in the Tab. These are considered to be the existing modulation techniques. Vertical transporter dispersion and even bearer dissemination are the two broad categories of MCS PWM control methods [2]. Fig. 6 shows the unipolar MCSPWM switching pattern. It is elevated to trigger the DC-connect switches of CDDCLC.
In this proposed work, a unipolar sine and trapezoidal reference with a triangular transporter is utilized to produce terminating beats for a 15 level inverter. For m-level inverter utilizing unipolar multi-bearer systems, (m−1)/2 transporters with a similar recurrence fc and same top to-top plentifulness Ac are utilized. The reference waveform has adequacy Am and recurrence fm and it is put at the zero reference. The reference wave is ceaselessly contrasted and every one of the transporter signals On the off chance that the reference wave is in excess of a bearer signal, at that point the dynamic gadgets comparing to that transporter are turned on.
The proposed PWM is delineated in Figs. 6 and 7. It includes four three-sided transporters and two reference signals (sine wave) for PWM age and the relating simple hardware for base PWM age for each level as depicted in Fig. 7. The reference wave is consistently contrasted and every one of the transporter signals. On the off chance that the reference wave is in excess of a transporter signal, at that point the dynamic gadgets comparing to that bearer are turned on. Otherwise, the devices are switched off. The frequency of the carrier signal determines the frequency of the AC voltage waveform. And the magnitude of the reference signal determines the effective RMS value of the output voltage waveform.

MATLAB Simulation Results
To validate the proposed method, simulation results summarized in this section have been obtained with a single-phase 15-level CDDCLC using MATLAB/Simulinkenvironment as shown in Figs. 8-10. The simulation conditions are shown in Tab. 2. Fig. 8 illustrates the inverter output voltage of level generation unit and the common H Bridge. As a steady-state response, the current waveform for a resistive load is also shown in Fig. 9. In this case, the fs is kHz with the output frequency of 50 Hz.
Simulation results show that the line-to-neutral voltage THD is 6.73% for the proposed 15 level CDDCLC. This confirms the improved power quality of increased output voltage.

Comparison of Hardware System Design
A CDDCLC from the DC input to AC output mainly consists of three parts: a chopper, a level generation unit, and common H Bridge. The power loss of the CDDCLC originates from the three parts. The IGBTs are selected for the chopper and multilevel inverter. Most of the power loss in the CDDCLC is due to the switching loss and the conduction loss of the IGBTs and diodes. The 1Ø CDDCLC configuration is intended and applied for 150 V (Vmax) output voltages. It is observed that the Controller and driver unit with CDDCLC constitute the implementation setup. Further, the DC input for the lift chopper units is derived from the supply of rectifier and battery banks. Here, the boost chopper is made up of HGTG20N100D2 insulated gate bipolar transistor (IGBT) switches and passive components (L1 = L2 = 2 mH and C1 = C2 = 100 μF). Tab. 3 represents the technical specifications of HGTG20N100D2 power IGBT and driver ICTLP250. Fig. 11 shows the experimental setup.  The control signs to the IGBT driver circuit are given by the microcontroller (ATmega328). The driver circuit is designed using the driver IC from Toshiba-TLP250. HGTG20N100D2 power IGBT switches used in fabricating the DCLM and H-bridge inverter systems. Isolation and amplification processes are provided by the driver circuit using TLP250. Tab. 4 shows the technical specifications of driver IC TLP250.   Switching time t pLH /t pHL 0.5 μs (max) 6 Isolation voltage 2500 Vrms (min) The hardware results show that the line-to-neutral voltage is 139.9 V as shown in Fig. 12 and the THD is 9.7% as shown in Fig. 13 for the proposed 15 level CDDCLC. It shows the improved power quality performance of output voltage.    Tab. 7 shows simulated harmonic analysis of proposed BDCLCMLI. From the examination voltage harmonics from 8.45%( BDCLCMLI) to 6.73%( Proposed BDCLCMLI). Fig. 15 illustrates the qualitative analysis of proposed BDCLCMLI with other relevant works. The chart demonstrates the improvement of boundaries to be specific number switches, number of sources and voltage stress.

Conclusion
In this paper single-stage fifteen levels DC-interface converter (CDDCLC) is proposed for sun oriented photovoltaic (PV) applications. The proposed topology is incorporated with support DC chopper and Hconnect inverter to optimize the power converter to achieve the minimum harmonic profile. In examination with the traditional inverter frameworks, the proposed framework is utilized with decreased voltage stress, reduced switch check and DC source count. The proposed research work with CDDCLC configuration requires three DC sources for synthesizing fifteen-level AC output. This exploration structure is emphatically suggested for power converters utilized in UPS and drive applications since it is very economical. A reproduction and model of fifteen-level CDDCLC geography shows its total execution. This investigation structure switching technique is phase opposition and disposition pulse width modulation technique (POPD) which results in improved quality of obtained output AC power with 6.73% THD.
Funding Statement: The authors received no specific funding for this study.

Conflicts of Interest:
The authors declare that they have no conflicts of interest to report regarding the present study.