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Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Reeya Agrawal1,*, Anjan Kumar1, Salman A. AlQahtani2, Mashael Maashi3, Osamah Ibrahim Khalaf4, Theyazn H. H. Aldhyani5

1 VLSI Center of Excellence, GLA University, Mathura, 281406, India
2 Computer Engineering Department, Research Chair of New Emerging Technologies and 5G Networks and Beyond, College of Computer and Information Sciences, King Saud University, Saudi Arabia
3 Software Engineering Department, King Saud University, Riyadh, 11543, Saudi Arabia
4 Al-Nahrain University, Al-Nahrain Nano-Renewable Energy Research Center, Baghdad, Iraq
5 Applied College in Abqaiq, King Faisal University, Al-Ahsa, 31982, Saudi Arabia

* Corresponding Author: Reeya Agrawal. Email: email

TSP_CMC_29019.pdf

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