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High Precision SAR ADC Using CNTFET for Internet of Things

V. Gowrishankar1,*, K. Venkatachalam1

Department of ECE, Velalar College of Engineering and Technology, Erode, 638012, India.

* Corresponding Author: V. Gowrishankar. Email: email.

Computers, Materials & Continua 2019, 60(3), 947-957.


A high precision 10-bit successive approximation register analog to digital converter (ADC) designed and implemented in 32nm CNTFET process technology at the supply of 0.6V, with 73.24 dB SNDR at a sampling rate of 640 MS/s with the average power consumption of 120.2 μW for the Internet of things node. The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction logic. These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and noise level are within the limit. The proposed architecture has high scalability to CNTFET technology and also has higher energy efficiency. We compared the results of CNTFET based SAR ADC with other known architectures and confirm that this proposed SAR ADC can provide higher precision, power efficiency to the Internet of things node.


Cite This Article

APA Style
Gowrishankar, V., Venkatachalam, K. (2019). High precision SAR ADC using CNTFET for internet of things. Computers, Materials & Continua, 60(3), 947-957.
Vancouver Style
Gowrishankar V, Venkatachalam K. High precision SAR ADC using CNTFET for internet of things. Comput Mater Contin. 2019;60(3):947-957
IEEE Style
V. Gowrishankar and K. Venkatachalam, "High Precision SAR ADC Using CNTFET for Internet of Things," Comput. Mater. Contin., vol. 60, no. 3, pp. 947-957. 2019.

cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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