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Identifying and Verifying Vulnerabilities through PLC Network Protocol and Memory Structure Analysis

Joo-Chan Lee1, Hyun-Pyo Choi1, Jang-Hoon Kim1, Jun-Won Kim1, Da-Un Jung1, Ji-Ho Shin1, Jung-Taek Seo1, *

1 Department of Information Security Engineering, Soonchunhyang University, Asan, 31538, Korea.

* Corresponding Author: Jung-Taek Seo. Email: email.

Computers, Materials & Continua 2020, 65(1), 53-67. https://doi.org/10.32604/cmc.2020.011251

Abstract

Cyberattacks on the Industrial Control System (ICS) have recently been increasing, made more intelligent by advancing technologies. As such, cybersecurity for such systems is attracting attention. As a core element of control devices, the Programmable Logic Controller (PLC) in an ICS carries out on-site control over the ICS. A cyberattack on the PLC will cause damages on the overall ICS, with Stuxnet and Duqu as the most representative cases. Thus, cybersecurity for PLCs is considered essential, and many researchers carry out a variety of analyses on the vulnerabilities of PLCs as part of preemptive efforts against attacks. In this study, a vulnerability analysis was conducted on the XGB PLC. Security vulnerabilities were identified by analyzing the network protocols and memory structure of PLCs and were utilized to launch replay attack, memory modulation attack, and FTP/Web service account theft for the verification of the results. Based on the results, the attacks were proven to be able to cause the PLC to malfunction and disable it, and the identified vulnerabilities were defined.

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APA Style
Lee, J., Choi, H., Kim, J., Kim, J., Jung, D. et al. (2020). Identifying and verifying vulnerabilities through PLC network protocol and memory structure analysis. Computers, Materials & Continua, 65(1), 53-67. https://doi.org/10.32604/cmc.2020.011251
Vancouver Style
Lee J, Choi H, Kim J, Kim J, Jung D, Shin J, et al. Identifying and verifying vulnerabilities through PLC network protocol and memory structure analysis. Comput Mater Contin. 2020;65(1):53-67 https://doi.org/10.32604/cmc.2020.011251
IEEE Style
J. Lee et al., "Identifying and Verifying Vulnerabilities through PLC Network Protocol and Memory Structure Analysis," Comput. Mater. Contin., vol. 65, no. 1, pp. 53-67. 2020. https://doi.org/10.32604/cmc.2020.011251



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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