Table of Content

Open Access iconOpen Access

ARTICLE

Numerical Simulation of Fatigue Crack Growth in Microelectronics Solder Joints

K. Kaminishi1, M. Iino2, H. Bessho2, M. Taneda3

Department of Mechanical Engineering, Yamaguchi University, 2557 Toki-wadai, Ube City, 755-8611, Japan
Department of Mechanical Engineering, Yamaguchi University, 2557 Toki-wadai, Ube City, 755-8611, Japan
Department of Mechanical Engineering, Fukuyama University, GakuenCho 1, Fukuyama City, 729-0292, Japan

Computer Modeling in Engineering & Sciences 2000, 1(1), 107-110. https://doi.org/10.3970/cmes.2000.001.107

Abstract

An FEA (finite element analysis) program employing a new scheme for crack growth analysis is developed and a prediction method for crack growth life is proposed. The FEA program consists of the subroutines for the automatic element re-generation using the Delaunay Triangulation technique, the element configuration in the near-tip region being provided by a super-element, elasto-inelastic stress analyses, prediction of crack extension path and calculation of fatigue life. The FEA results show that crack extension rate and path are controlled by a maximum opening stress range, Δσθmax, at a small radial distance of r = d, where d is chosen to be a grain diameter's distance, 3.5 μm, in solder material. The experimentally obtained crack extension rate is found to be related to Δσθmax in FEA as da/dN = β[Δσθmax - γ]α, where α = 2.0, β = 4.5 × 10-9 mm5/N2 and γ = 98 M Pa are determined for all test conditions. The calculated values of crack extension life by the FEA using the above equation are in good agreement with the experimental ones and are independent of the joint types.

Keywords


Cite This Article

APA Style
Kaminishi, K., Iino, M., Bessho, H., Taneda, M. (2000). Numerical simulation of fatigue crack growth in microelectronics solder joints. Computer Modeling in Engineering & Sciences, 1(1), 107-110. https://doi.org/10.3970/cmes.2000.001.107
Vancouver Style
Kaminishi K, Iino M, Bessho H, Taneda M. Numerical simulation of fatigue crack growth in microelectronics solder joints. Comput Model Eng Sci. 2000;1(1):107-110 https://doi.org/10.3970/cmes.2000.001.107
IEEE Style
K. Kaminishi, M. Iino, H. Bessho, and M. Taneda "Numerical Simulation of Fatigue Crack Growth in Microelectronics Solder Joints," Comput. Model. Eng. Sci., vol. 1, no. 1, pp. 107-110. 2000. https://doi.org/10.3970/cmes.2000.001.107



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • 1575

    View

  • 1268

    Download

  • 0

    Like

Related articles

Share Link