Constant-Time Symmetry Exploitation for NTT Twiddle Factors in ML-KEM: A Unified Cost Model for Embedded Deployments

1  Introduction

The transition of Post-Quantum Cryptography (PQC) from theory to standardization has culminated in the adoption of ML-KEM (FIPS 203) by NIST [1,2]. While ML-KEM provides a strong security foundation, deployment on resource-constrained edge devices such as embedded sensors and smart cards still faces major efficiency challenges. The Number Theoretic Transform (NTT), which accelerates polynomial multiplication in the ring ℛq=Zq[X]/(X256+1), is the primary computational and storage bottleneck [3]. On low-power platforms such as ARM Cortex-M and RISC-V, NTT optimization is not only a speed problem; it is a joint trade-off among latency, memory footprint, energy, and side-channel risk.

Despite extensive research, practical ML-KEM implementations still face two unresolved problems. First, twiddle-factor management presents a difficult storage-latency dilemma. Full-table storage (Sfull) maximizes speed but consumes substantial ROM (512 bytes), which is costly on low-end microcontrollers; in contrast, on-the-fly generation (Sgen) minimizes storage but introduces high computational overhead [4,5]. Although some FPGA accelerators exploit twiddle symmetry to reduce block RAM usage [6,7], these solutions are often hardware-specific and not directly portable to software [8,9]. In software, naive half-table realizations may introduce timing variability when implemented with conditional branches, especially if the branch condition becomes secret-dependent in a broader implementation context; this motivates a portable branchless formulation with explicit proof obligations. Second, a unified quantitative evaluation framework is still missing. Prior studies are often platform-specific and fragmented, without a formal model to jointly evaluate ROM, RAM, ALU cycles, energy, and side-channel risk. Without such a model, system architects are forced to use ad-hoc trial-and-error rather than principled hardware-aware selection.

To address these gaps, this paper provides a structured and theory-backed examination of twiddle-factor symmetry for ML-KEM NTT. The main contributions are as follows:

•   A Constant-Time Shalf Strategy with Formal Indexing Consistency: We propose a branchless, symmetry-based reconstruction method that halves table storage to 256 bytes, and we provide a formal statement linking the implemented rule (k & 0x7F plus sign mask) to the target twiddle sequence.

•   A Device-Aware Memory-Arithmetic Trade-off (MAT) Model: We establish a generalizable weighted-cost model that quantifies ROM, RAM, arithmetic latency, energy, and side-channel risk under an explicit threat model, and separates model definition from empirical calibration.

•   Empirical Evidence with Cross-Platform Validation: We provide controlled measurements on ARM Cortex-M4, RISC-V, and x86, and show that empirical best-strategy outcomes align with MAT predictions under platform-specific constraints.

The remainder of this paper is organized as follows. Section 2 reviews related NTT optimization work. Section 3 introduces mathematical preliminaries. Section 4 presents the constant-time branchless half-table reconstruction strategy (Shalf) with formal indexing consistency. Section 5 introduces the MAT model and robustness protocol. Section 6 reports detailed measurements on Cortex-M4, RISC-V, and x86 with leakage-evidence summaries. Section 7 concludes.

2  Related Work

Given the central role of ML-KEM (and its predecessor CRYSTALS-Kyber) in NIST post-quantum standardization, research on NTT optimization has grown rapidly in recent years. Both academia and industry have reported substantial progress across ARM Cortex-M4 microcontrollers, RISC-V embedded platforms, x86-64 high-performance systems, and FPGA accelerators. These studies have advanced lattice-based cryptography from theory to deployment, while also exposing unresolved gaps in unified storage-computation-energy-security trade-off modeling.

First, extensive optimization work has been reported on ARM Cortex-M4. Owing to its DSP features, Cortex-M4 is a primary reference platform for embedded PQC. Early work leveraged single-cycle DSP instructions (e.g., SMLAD) to accelerate butterfly operations [10], establishing the PQM4 framework as a benchmark [11]. Subsequent work introduced packed arithmetic and signed representations for memory-efficient high-speed implementations [12]. Later optimizations improved pipeline behavior through lazy reduction, instruction scheduling, and register allocation [13,14]. Although alternatives such as Plantard reduction reduce instruction counts [15], and masked implementations highlight side-channel risks in memory access [16], full-table twiddle storage still dominates software practice.

Second, RISC-V implementation paths combine software flexibility with modular ISA extensions. At the software level, researchers use the larger register file to cache coefficients and twiddle factors, reducing load/store overhead [17,18]. To overcome base-ISA limits, instruction extensions and accelerators (e.g., RANTT) compress NTT operations into fewer cycles [19,20]. With RISC-V vector extensions (RVV), recent studies focus on vectorized throughput scaling [21,22]. However, quantitative analysis of twiddle-storage area/energy cost and algebraic symmetry exploitation on baseline cores remains limited.

Third, on x86-64 platforms, optimization objectives shift from storage conservation to SIMD pipeline saturation. Seiler’s AVX2 implementation established the fully vectorized Montgomery-reduction paradigm with layout-aware tables [23]. In AVX-512-era designs, implementations often store multiple table layouts to reduce permutation overhead, increasing constant-memory usage [24]. Because high-performance processors benefit from deep caches [25,26] and suffer branch-misprediction penalties, branch-based index strategies are typically avoided. This storage-for-throughput philosophy contrasts with embedded targets and motivates a unified cross-platform trade-off model.

Finally, FPGA acceleration studies often split between high-throughput BRAM-based full-table designs [27] and low-area logic-centric designs. To reduce BRAM cost, several works propose twiddle-factor generators (TFGs) that compute factors on the fly. Frameworks such as NTTGen and SAM further demonstrate systematic NTT-core generation with flexible area-throughput trade-offs [28]. Recent high-performance NTT hardware accelerators also target standardized lattice schemes such as ML-KEM and ML-DSA [29]. However, these hardware-specific optimizations are usually not directly transferable to serial software execution, where equivalent generation logic can be prohibitively expensive.

In summary, while the literature demonstrates significant progress in NTT optimization, two critical gaps remain. First, a standardized constant-time software method for symmetry exploitation is still under-documented. Naive half-table realizations may introduce timing variability when implemented with conditional branches, especially if the branch condition becomes secret-dependent in a broader implementation context; meanwhile, hardware-specific optimizations often lack algorithmic transparency for direct software porting. Second, a unified quantitative evaluation framework is absent. Current research relies on empirical, platform-specific heuristics, lacking a formal model to analytically trade off storage, computation, and energy across heterogeneous architectures. This work addresses these deficiencies by establishing the MAT model and proposing a constant-time branchless half-table strategy.

3  Preliminaries

3.1 Polynomial Rings and Parameterization in ML-KEM

ML-KEM operates over the structured polynomial ring

ℛq=Zq[x]/(xn+1)(1)

where n=256 is the polynomial degree and q=3329 is a specific prime modulus. Elements of this ring are polynomials of degree at most n−1 with coefficients in the finite field Zq. Operations in this ring, specifically polynomial multiplication, form the foundation of the Matrix-Vector multiplication

As+e(2)

which constitutes the core Learning-With-Errors (LWE) hardness assumption. The modulus xn+1 is chosen specifically to enable the use of NTT. Because xn≡−1(modxn+1), this ring exhibits the neg-acyclic property, which is crucial because it allows the convolution theorem to be applied efficiently, provided appropriate roots of unity exist in the base field.

3.2 Number Theoretic Transform (NTT)

NTT is a linear map that transforms a polynomial from the coefficient domain to the value domain (or frequency domain). For a vector of coefficients a=(a0,…,an−1), NTT computes a^=NTT(a), where the multiplication of two polynomials a⋅b in ℛq corresponds to the pointwise multiplication a^∘b^ in the NTT domain. The algorithm employed is a variant of the Fast Fourier Transform (FFT). Specifically, ML-KEM uses a negacyclic NTT. The calculation is decomposed into log2⁡n layers. In each layer i, coefficients are paired and processed via “butterfly” operations. A Cooley-Tukey butterfly takes two inputs u,v and a twiddle factor ζ to produce:

u′=u+ζv(modq)v′=u−ζv(modq)(3)

The efficiency of NTT depends on rapid access to the twiddle-factor sequence ζ required at each layer.

4  A Constant-Time Twiddle Factor Reconstruction Method

Building upon the mathematical foundations in Section 3, we now address efficient twiddle-factor management. The key objective is to halve table storage while preserving deterministic control flow. In this section, we first define an implementation-consistent indexing rule (Section 4.1), then present a branchless accessor (Section 4.2), and finally discuss security scope and portability (Section 4.3).

4.1 Core Principle: Symmetry with Implementation-Consistent Indexing

For ML-KEM, q=3329 and q−1=13⋅256, so primitive 256-th roots of unity exist in Zq. Let ζ be a primitive 256-th root. Then:

ζ256≡1(modq),(4)

ζ128≡−1(modq).(5)

Hence, for any exponent u∈[0,127]:

ζu+128=ζu⋅ζ128≡−ζu(modq).(6)

This identity yields a direct half-table reconstruction rule. Define a canonical twiddle sequence Ω[k] (k∈[0,255]) such that Ω[k+128]≡−Ω[k](modq). Store only the first half in a table T[j]=Ω[j] for j∈[0,127]. For any k∈[0,255], write:

j=kmod128,b=⌊k128⌋∈{0,1}.(7)

Then:

Ω[k]≡(−1)b⋅T[j](modq).(8)

In implementation, j is computed as k & 0x7F and b as (k≫7) & 1, which is exactly equivalent for 8-bit bounded indices. For inverse NTT factors of the form ζ−u, the schedule first maps exponents to their modulo-256 index and then calls the same accessor; therefore the previously cited 128−u relation is a special case of this unified modulo-128 rule, not a competing rule.

Proposition 1 (Correctness of the branchless accessor): Let k∈[0,255], j=k & 0x7F, and b=(k≫7)&1. Define

R(k)={T[j],b=0,q−T[j],b=1.

Then R(k)≡Ω[k](modq).

Proof: If b=0, then k<128 and j=k, so R(k)=T[k]=Ω[k]. If b=1, then k=128+j and R(k)=q−T[j]≡−T[j]≡−Ω[j]≡Ω[j+128]=Ω[k](modq). Thus both cases satisfy R(k)≡Ω[k], proving correctness. □

4.2 Key Mechanism: Branchless Implementation

To avoid timing variability from conditional branches, we implement the selection logic with bitwise masking, as shown in Algorithm 1.

The logical decomposition of Algorithm 1 is shown in Table 1. The access mechanism operates as follows:

•   The mask variable is set to all ones (0xFFFF) when k≥128, otherwise it is all zeros.

•   val & ~mask: Returns val when mask = 0, and returns 0 when mask = 0xFFFF.

•   neg & mask: Returns 0 when mask = 0, and returns neg when mask = 0xFFFF.

•   Consequently: when k<128, the function returns val; when k≥128, the function returns neg, i.e., the sign-flipped symmetric value.

This scheme saves 50% of twiddle-factor ROM (256 bytes vs. 512 bytes) and preserves deterministic control flow. The trade-off is a small fixed arithmetic overhead from modular negation and mask operations. The strategy is therefore attractive for embedded systems with strict ROM limits.

4.3 Implementation Analysis: Security Scope and Portability

To justify the design choice of our bitwise masking approach, we compare it against alternative methods for realizing the half-table strategy. As summarized in Table 2, three primary implementation paradigms exist:

1.    Branch-Based Implementation (Timing-Variant): A naive approach uses conditional statements (if k≥128) to trigger modular negation. This may create data-dependent timing behavior if k is secret-dependent in a broader implementation context.

2.    Arithmetic-Shift Implementation (Portability Issues):Some “branchles” optimizations rely on the specific behavior of arithmetic right shifts (>>) to generate masks (e.g., mask=k>>15). However, the C standard leaves the behavior of right-shifting negative signed integers implementation-defined. This leads to portability hazards, where the code may function correctly on one compiler/architecture (e.g., GCC on x86) but fail on another (e.g., specific DSP compilers), limiting its utility in heterogeneous platforms.

3.    Proposed Bitwise Masking (Constant-Time Coding Pattern): Our strategy (Algorithm 1) utilizes deterministic logic operations (&, |, ∼) combined with subtraction. This design achieves two engineering goals:

•   Constant-time coding discipline: the high-level instruction path is input-independent (subject to compiler/backend realization).

•   Strict portability: It relies solely on standard boolean logic defined consistently across all C99-compliant compilers and architectures.

By avoiding explicit branching and implementation-defined signed shifts, the proposed method provides a robust baseline for secure engineering practice. We inspected the compiled binary (using arm-none-eabi-objdump) for the ARM Cortex-M4 target. The masking logic compiles strictly to deterministic arithmetic and bitwise instructions (e.g., AND, EOR, RSB), with no data-dependent branching (B or IT blocks) generated by the compiler. Full side-channel security still requires empirical leakage assessment under an explicit threat model, which we discuss in Section 6.

5  MAT: Unified and Generalizable Cost Model

Having presented the constant-time implementation of the half-table strategy (Shalf) in Section 4, a fundamental engineering question remains: how does one rigorously determine the optimal strategy for a specific hardware target? While qualitative comparisons suggest that Shalf offers a balance, relying on intuition or ad-hoc benchmarks is insufficient for heterogeneous platforms where constraints on ALU, ROM, RAM, energy vary drastically and security. To address this, we propose the Memory-Arithmetic Trade-off (MAT) Model, a unified analytical framework designed to quantify the decision-making process. In this section, we first establish a formal representation of the strategy space (Section 5.1), then derive multi-dimensional cost functions covering storage, latency, energy, and security (Section 5.2). Finally, we introduce device-sensitivity parameters to formulate a platform-aware optimization objective (Section 5.3), enabling precise, mathematical strategy selection. The proposed MAT model is positioned as a device-aware engineering cost model for a finite strategy set, and its purpose is to provide an interpretable strategy-selection framework.

5.1 Unified Representation of Twiddle-Factor Strategies

To enable rigorous comparison, we first formalize the implementation variants as a set 𝒮:

𝒮={Sfull, Shalf, Sgen}.(9)

where Sfull denotes the full-table storage strategy, Shalf denotes the proposed symmetry-based half-table storage strategy, and Sgen denotes the on-the-fly generation strategy.

Each strategy S∈𝒮 is mapped to a multi-dimensional cost vector C(S) that captures its resource footprint:

C(S)=(CROM(S), CRAM(S), CALU(S), Cene(S),Csec(S))(10)

Here, the components represent ROM usage (bytes), RAM usage (bytes), ALU latency (cycles), Energy consumption (Joules), and Security cost (side-channel risk level) respectively. This abstraction provides the foundation for the quantitative trade-off analysis in the subsequent sections.

5.2 Formal Multi-Dimensional Cost Model

To quantify the strategies in 𝒮, we define explicit cost functions for ROM, RAM, ALU latency, energy, and security.

Firstly, in order to quantify the usage of read-only memory for different strategies, we define a ROM cost function to capture the static storage requirements. The ROM cost of S is defined as:

CROM(S)={n⋅w,S=Sfull,n2⋅w,S=Shalf,0,S=Sgen(11)

where n is the total twiddle factors count, w is is the word size, CROM(Sfull)=n⋅w represents that the ROM cost n⋅w corresponds to storing the complete, precomputed table for Sfull, which is characterized by the highest ROM usage but provides the fastest access speed, making it suitable for applications that require high performance and sufficient memory. CROM(Shalf)=n2⋅w represents that the term n2⋅w reflects the 50% storage reduction achieved by exploiting the symmetry ζ128≡−1 for Shalf, which is characterized by that the ROM occupation is halved, but additional arithmetic operations are required to achieve a balance between storage and calculation. CROM(Sgen)=0 indicates that the ROM cost is 0, as no table is stored and is generated by calculation each time it is needed for Sgen.

Secondly, to quantify the usage of RAM for different strategies, we define a RAM cost function to capture the working memory requirements. The RAM cost of S is defined as:

CRAM(S)={0,S=Sfull,m⋅w,S=Shalf,2m⋅w,S=Sgen(12)

where m represents the total temporary variables count. CRAM(Sfull)=0 indicates requiring zero additional runtime RAM for Sfull, which requires the minimum working memory and only the target memory location. CRAM(Shalf)=m⋅w indicates m⋅w accounts for the RAM need to store the mask and negated value for Shalf. CRAM(Sgen)=2m⋅w indicates that the RAM cost 2m⋅w is maximized to maintain the state variables for Sgen.

Thirdly, to quantify the computational latency of different strategies, we define a ALU latency cost function to capture the time performance. The ALU latency cost of S is defined as:

CALU(S)={tmem,S=Sfull,tmem+tadd,S=Shalf,ttrig+2tmult+tadd,S=Sgen.(13)

Here, top denotes the latency of memory access (mem), addition (add), multiplication (mult), and trigonometric generation (trig). Clat(Sfull)=tmem represents that the cost is bounded strictly by tmem for Sfull, which represents a pure memory lookup with no arithmetic overhead. Clat(Shalf)=tmem+tadd represents a hybrid cost for Shalf, which fetches a base factor (tmem) followed by a modular subtraction (tadd) to reconstruct the symmetric entry. Clat(Sgen)=ttrig+2tmult+tadd represents that the term ttrig+2tmult+tadd captures the high algorithmic overhead of synthesizing factors on-the-fly for Sgen, which involves complex modular multiplications and additions.

Fourthly, to quantify the energy consumption for different strategies, we define an energy cost function to capture the power consumption. The energy cost of S is defined as:

Cene(S)={emem,S=Sfull,emem+eadd,S=Shalf,etrig+2emult+eadd,S=Sgen.(14)

Here, eop denotes the latency of memory access (mem), addition (add), multiplication (mult), and trigonometric generation (trig). Cene(Sfull)=emem represents that energy consumption is dominated by the memory subsystem for Sfull, while arithmetic energy is zero, static leakage from the large ROM and dynamic energy from frequent read operations constitute the total cost. Cene(Shalf)=emem+eadd represents that balances memory and computation. It reduces static ROM leakage by half compared to Sfull, replacing the saved memory energy with the typically lower energy cost of simple arithmetic operations (negation). Cene(Sgen)=etrig+2emult+eadd represents eliminating static ROM energy entirely but incurs the highest dynamic power consumption due to the continuous activity of the multiplier and ALU units required for complex factor generation.

Finally, to quantify the security-related implementation risk of different strategies, we define a security cost function to capture residual leakage risk under the stated threat model. This term is defined as a residual leakage-risk penalty. A larger value means higher residual risk, and a smaller value means lower residual risk. The security cost of S is defined as:

Csec(S)={ρbranch,S=Sfull,ρhalf,S=Shalf,ρgen,S=Sgen.(15)

Here, 1≥ρbranch>ρhalf,ρgen≥0. The symbol ρ denotes a threat-model-dependent residual leakage-risk score rather than a binary “secure/insecure” label. This definition keeps the model direction consistent: lower Csec means lower residual side-channel risk. Here, ρbranch, ρhalf, and ρgen denote residual leakage-risk penalties associated with the full-table, half-table, and on-the-fly generation strategies, respectively. The ordering ρbranch>ρhalf,ρgen reflects that branch-based or input-dependent access patterns may lead to higher residual timing/cache risk under the stated threat model, whereas branchless reconstruction and generation-based strategies are assigned lower residual risk. These parameters are not interpreted as absolute security guarantees; they provide a model-level risk penalty used for comparative strategy selection.

5.3 Device-Aware Optimization Framework

To generalize the evaluation across heterogeneous platforms (e.g., IoT microcontrollers vs. high-performance servers), we introduce a parameterized optimization framework. This maps the absolute costs derived in Section 5.2 to a relative, platform-specific utility value.

1) Hardware Sensitivity Vector (θ). We define a device-class sensitivity vector θ to capture the inherent resource constraints of the target hardware as:

θ=(θROM, θALU, θRAM, θene,θsec)(16)

Here, each component θk∈[0,1] quantifies the scarcity or cost of a specific resource on a given device. θROM/θRAM represents memory scarcity. A high value (e.g., ≈1.0) characterizes deeply embedded 8-bit/16-bit MCUs where Flash/SRAM is the primary bottleneck. θALU represents the “penalt” of computation. High values apply to simple cores without hardware multipliers, while low values apply to DSP-enhanced cores (like Cortex-M4). θene is Quantifying energy sensitivity, critical for battery-powered IoT nodes but negligible for mains-powered servers. θsec reflects the threat model. High values indicate security-critical deployments (e.g., smart cards) requiring strict side-channel resistance.

2) Hardware Sensitivity Weights function (ω(θ)). We define the hardware sensitivity weights function ω(θ) which represent the relative importance of different cost dimensions under specific hardware platform parameters θ, and maps objective hardware parameters to subjective optimization weights. It defines ‘how to balance based on hardware characteristics’. ω(θ) is a set, it is defined as follows.

ω(θ)={ωROM(θ),ωRAM(θ),ωALU(θ),ωene(θ),ωsec(θ)}(17)

where ωROM(θ) is a storage space weight used to measure the scarcity of ROM/Flash storage space. Its high value scenarios are in 8-bit/16 bit MCUs and embedded devices with Flash < 64 KB, while low value scenarios are in x86 servers and platforms with ample storage. The greater the weight, the more inclined one is to choose strategies with lower storage costs. ωRAM(θ) is the weight of running memory, used to measure the tightness of RAM resources. Its high value scenarios are deeply embedded devices with only a few KB of SRAM, while low value scenarios are desktop/server platforms with large capacity RAM. This weight affects optimization choices that affect runtime memory allocation. ωALU(θ) is the computational power weight used to measure the relative cost of ALU computation operations. Its high value scenarios are low-power MCUs (slow computation, high energy consumption), while low value scenarios are high-performance CPUs (fast computation, low energy consumption). The smaller the weight, the more tolerant it is to computationally intensive strategies. ωene(θ) is an energy sensitivity weight used to measure the importance of energy consumption. Its high value scenarios include battery powered IoT devices and energy harvesting systems; while low value scenarios refer to plug-in devices and platforms with stable power sources. This weight affects the balance of energy efficiency. ωsec(θ) is a security requirement weight used to measure the importance of side channel security. Its high value scenarios refer to payment terminals, military equipment, and security critical systems, while low value scenarios refer to ordinary devices for non sensitive data processing. This weight determines whether to implement with constant time.

Secondly, how is ω(θ) designed? ω(θ) is a conversion function which accepts objective hardware parameters θ and outputs the subjective importance (weight) assigned to each dimension during optimization. Its design embodies the optimization philosophy of ‘where scarce, save’. In practical applications, the specific form of ωsec(θ) is flexible, it is likely to be a more complex mapping, even based on empirical data (benchmark testing) lookup tables, but its core idea remains unchanged: to adapt the optimization strategy to the characteristic parameters of the hardware platform. For example, we can design a simple linear function as follows.

{ωROM(θ)=αROM⋅θROMωALU(θ)=αALU⋅θALUωRAM(θ)=αRAM⋅θRAMωene(θ)=αene⋅θeneωsec(θ)=αsec⋅θsec(18)

where α is the scaling factor. In this linear model, empirical coefficients are used to adjust the importance of different dimensions, and their values are set by the designer based on overall optimization objectives such as “extreme space saving” and “ultimate performance”. We use the linear weighting function in this model as an interpretable engineering instance, and the stability of the resulting recommendation is evaluated through exhaustive weight perturbation and sensitivity analysis in Section 6.

3) Weighted Objective Function (Φ(S;θ)). To select the optimal strategy, we formulate the problem as the minimization of a total cost function Φ(S;θ). We map the sensitivity parameters θ to normalized optimization weights ω(θ):

Φ(S;θ)=∑k∈𝒦ωk(θ)⋅Ck(S)(19)

where 𝒦={ROM,RAM,ALU,ene,sec}. The weights ωk(θ) are typically derived via a linear mapping ωk∝αk⋅θk, where αk are system-level scaling factors. For example, on ultra-low-cost 8-bit microcontrollers, the dominating weight is often wROM(θ), because flash reads are expensive and ROM capacity is extremely limited. In contrast, on latency-sensitive ARM Cortex-M designs, wlat(θ) typically dominates, whereas DSP-oriented or RISC-V vector platforms assign comparatively small weights to arithmetic costs, favoring on-the-fly twiddle generation.

4) Optimal Strategy Selection. The optimal twiddle-factor management strategy S∗ for a specific hardware platform is formally defined as the strategy that minimizes the hardware-weighted objective:

S∗(θ)=arg⁡minS∈𝒮Φ(S;θ)(20)

This scalar objective is used for hardware-aware strategy selection over the finite strategy set 𝒮. In the multi-objective sense, Pareto dominance is interpreted in the standard way: a strategy Sa dominates Sb only if Ck(Sa)≤Ck(Sb) for all cost dimensions and the inequality is strict for at least one dimension. Therefore, this paper reports Shalf as a Pareto-efficient embedded compromise or knee point under the tested cost model, rather than as an unconditional globally Pareto-optimal solution. This formulation allows the MAT-Model to dynamically predict the best strategy: favoring Shalf on constrained IoT devices (high θROM, high θsec) while potentially favoring Sfull on high-performance servers (low θROM, low θALU). This formulation highlights a key observation: unlike fixed implementation heuristics, the optimal strategy is not universal but varies systematically with hardware characteristics. The parameterized objective function thus provides a principled and portable method for selecting between full-table storage, half-table storage with modular negation, and on-the-fly generation.

In subsequent sections, we validate this optimization framework empirically across diverse platforms, demonstrating that hardware-weighted cost modeling accurately predicts the most efficient strategy in practice.

6  Experimental Results and Analysis

This section evaluates the practical viability of twiddle-factor symmetry exploitation in ML-KEM. We evaluate the strategies across all three platforms (ARM Cortex-M4, RISC-V, and x86-64) to compare Sfull, Shalf, and Sgen under a unified C framework. This provides comprehensive cross-platform empirical evidence to validate the MAT model’s predictions.

6.1 Experimental Setup

To ensure a rigorous evaluation that is both internally consistent for model validation and comparable to the state-of-the-art, we established a unified experimental framework. Our methodology isolates the algorithmic impact of twiddle-factor strategies while benchmarking their absolute performance against existing high-speed and masked implementations.

1)   Target Platforms and Compilation Environments. We selected three platforms representing embedded and high-performance settings. In this revision, all three platforms (P1/P2/P3) are measured under a unified benchmark configuration. Table 3 lists hardware specifications and toolchains.

•   Platform P1 (Embedded IoT): STMicroelectronics STM32F407 (ARM Cortex-M4) operating at 168 MHz with 192 KB SRAM. As the primary embedded PQC reference, this platform is our main target for memory-constrained trade-off analysis. Code was compiled using arm-none-eabi-gcc (v10.3) with -O3.

•   Platform P2 (Open ISA Edge): SiFive HiFive1 Rev B (RISC-V FE310-G002) operating at 320 MHz. We used riscv64-unknown-elf-gcc (v10.2) with -O3.

•   Platform P3 (High-Performance): Intel Core i7-12700K (x86-64 AVX2). Code was compiled using gcc (v9.4) with -O3.

2)   Implementation Strategies. To satisfy the dual objectives of theoretical model validation and practical benchmarking, we classify our implementations into two categories:

a.  Controlled Strategy Variants (Internal Comparison). To validate the MAT-Model (Section 5), we implemented the three core strategies within a unified C-language framework derived from the pqm4 and pqriscv libraries. This ensures that observed performance differences arise solely from the storage strategy rather than disparate assembly optimizations.

•   Sfull (Baseline): Uses the standard precomputed lookup table (512 bytes). The array structure remains unchanged from the reference implementation.

•   Shalf (Proposed): Reduces the table to 128 entries (256 bytes). Accessor macros are replaced with our proposed inline constant-time reconstruction logic (Algorithm 1) to handle indices k≥128 without branching.

•   Sgen (on-the-fly): Removes the data table entirely. Twiddle factors are computed dynamically via a next_zeta() state machine added to the NTT loop.

b.  Reference Baselines (State-of-the-Art Comparison): To assess practical competitiveness, we benchmark our controlled variants against established high-performance implementations:

•   PQM4 (Botros et al. [12]): Highly optimized assembly implementation, used here as a practical speed reference for Sfull.

•   Optimized Stack (Abdulrahman et al. [13]): A further refined assembly implementation focusing on register allocation and instruction scheduling.

•   Masked Proxies (Kannwischer, [14]): To evaluate security-performance trade-offs, we reference standard masking overheads (typically 30%–100%) reported in [14] as a baseline for achieving side-channel resistance.

3)   Measurement Methodology. All strategies on all three platforms were evaluated using the same test harness to ensure fairness.

•   Cycle Counts (ALU): Measured by hardware performance counters with interrupts disabled.

•   Memory Footprint: Compiled with GCC -O3. ROM (.text +.rodata) and stack usage were extracted via the size utility and static analysis.

•   Energy Consumption: For P1 and P2, measured directly via external instrumentation (ST-Link V3 power bridge with a shunt resistor). For P3 (x86-64), energy was estimated using Intel RAPL (Running Average Power Limit) software counters.

•   Security Analysis: We report constant-time coding properties, static branchlessness checks, and an empirical leakage-evaluation protocol (timing traces and TVLA) rather than a blanket security proof.

Assembly-level branchlessness check. We additionally inspected the generated Cortex-M4 assembly using arm-none-eabi-objdump -d under the tested -O3 configuration. The twiddle accessor was compiled into a fixed sequence of shift, mask, subtraction, and logical instructions, and no data-dependent conditional branch was observed for the selection path. This check supports the constant-time coding claim for the tested compiler/backend configuration, while not replacing empirical leakage evaluation.

4) Threat Model and Verification Scope. We adopt a first-order timing/power leakage threat model in which an attacker can collect repeated traces of the same operation and perform statistical distinguishers. The goal of this work is to reduce implementation-level leakage risk in twiddle-factor access by enforcing branchless control flow. Therefore, statements in this section are interpreted as follows: (i) constant-time coding property at source/assembly level, and (ii) empirical leakage evidence when timing traces or TVLA are available. We do not claim that branchless twiddle access alone yields complete side-channel security against all leakage classes.

6.2 Comprehensive Five-Dimensional Strategy Comparison

This subsection reports detailed Cortex-M4 measurements. We first compare the three controlled variants (Sfull, Shalf, Sgen) in one C framework, then position results against external assembly baselines. The comparison spans latency, storage, memory, energy, and side-channel-risk indicators.

1) Computational Latency Analysis

We begin by evaluating execution performance (cycles per NTT) on the Cortex-M4 platform, as shown in Fig. 1.

Figure 1: Implementation cycle count comparison for NTT of ML-KEM.

Data in Table 4 shows that, within the same C framework, Shalf incurs about 3.2% overhead (3226 vs. 3125 cycles) over Sfull. This indicates that branchless reconstruction adds only a small fixed arithmetic cost. Against highly optimized assembly baselines, the C implementation remains close (about 5.8% over PQM4 baseline), which is sufficient for controlled model validation.

2) Storage Footprint Analysis (ROM & RAM)

As depicted in Fig. 2 and Table 5, Shalf achieves its primary goal: a 50% reduction (256 bytes) in .rodata relative to both the internal Sfull baseline and typical external SOTA implementations. This corresponds to an overall ROM reduction of about 8%. Although Sgen removes the table entirely, it introduces notable code inflation (about 330 bytes) due to state-machine logic. Consequently, its total footprint (2120 bytes) provides only limited benefit over Shalf (2140 bytes), supporting Shalf as a balanced software strategy.

Figure 2: ROM footprint analysis.

Table 6 and Fig. 3 analyze runtime stack usage. Internally, Shalf introduces a modest fixed stack increase (+16 B). Compared with typical masked implementations requiring substantially larger state, this overhead remains small for embedded deployment. The bold percentages in Table 6 indicate the relative increase in stack usage compared with the Sfull baseline of approximately 80 B. Specifically, Shalf requires an additional 16 B (+20%) for the branchless reconstruction variables, whereas Sgen requires approximately 48 B more (+60%) to maintain the factor-generation state.

Figure 3: RAM footprint analysis.

3) Energy Consumption Analysis

Fig. 4 and Table 7 show that energy trends follow runtime trends. On Cortex-M4, Shalf adds about 3.3% energy over Sfull, while Sgen adds 77.6%. The masking entry is an inferred reference point and is used only for directional comparison.

Figure 4: Energy consumption comparison.

4) Security and Side-Channel Risk Comparison

As summarized in Fig. 5 and Table 8, Shalf provides a favorable compromise: lower timing/cache risk indicators than branch-based lookup at far lower overhead than full masking or on-the-fly generation. These results should be interpreted as implementation-risk evidence under the stated threat model, not as a complete side-channel proof.

Figure 5: Approximate side-channel risk vs. overhead comparison.

6.3 Validation of the MAT Model

We validate MAT on Cortex-M4 using the measured data above and the consistent security-cost definition from Section 5.

Step 1: Platform vector (θ).

θ=(θROM:0.9, θRAM:0.3, θALU:0.6, θene:0.8, θsec:0.7).(21)

Step 2: Normalized cost vectors C(S).

C(Sfull)=(1.0, 0.1, 0.112, 0.475, 1.0),(22)

C(Shalf)=(0.5, 0.15, 0.116, 0.491, 0.3),(23)

C(Sgen)=(0.0, 0.2, 1.0, 1.0, 0.25).(24)

Step 3: Weight vector (ω). Using αROM=1.0, αRAM=0.5, αALU=0.7, αene=0.7, and αsec=0.6, we obtain:

ω=(ωROM:0.367, ωRAM:0.061, ωALU:0.171, ωene:0.229, ωsec:0.171).(25)

Step 4: Total cost computation.

Φ(Sfull)=0.672,(26)

Φ(Shalf)=0.376,(27)

Φ(Sgen)=0.455.(28)

The resulting MAT scores, prediction ranks, and measured ranks are summarized in Table 9, where Shalf obtains the lowest MAT cost and is ranked first by the model, consistent with the measured Cortex-M4 ranking.

Sensitivity analysis. To evaluate whether the MAT recommendation depends on a single manually selected weight setting, we perturbed each weight scale αk over {0.6,0.8,1.0,1.2,1.4}. Since the MAT model contains five cost dimensions, namely ROM, RAM, ALU latency, energy, and security risk, the perturbation set contains 55=3125 weight-scale combinations.

For each weight-scale combination α, we recomputed the normalized weights ωk(θ,α) and then evaluated the MAT objective value

Φ(S;θ,α)=∑k∈𝒦ωk(θ,α)Ck(S)(29)

For each combination, the strategy with the smallest objective value was recorded as

S∗(θ,α)=argminS∈𝒮⁡Φ(S;θ,α),(30)

where 𝒮={Sfull,Shalf,Sgen}. The value 3072 was obtained by counting the number of perturbation combinations for which S∗(θ,α)=Shalf, namely

|{α: S∗(θ,α)=Shalf}|=3,072.(31)

Therefore, across all 3125 offline sensitivity-analysis combinations, Shalf was selected as the minimum-cost strategy in 3072 cases, corresponding to

3,0723,125=98.3%.(32)

This result indicates that the MAT recommendation remains highly robust under weight perturbation rather than depending on one specific tuning setting.

6.4 RISC-V and x86 Empirical Results

To complete cross-platform validation, Tables 10 and 11 present the measured outcomes on P2 and P3 and the MAT prediction–empirical outcome alignment across the three platforms. The purpose of this subsection is to verify whether the proposed MAT model can explain strategy selection beyond a single Cortex-M4 device. In particular, we examine whether ROM-sensitive embedded platforms favor Shalf, while high-performance SIMD-oriented platforms may favor Sfull due to lower ROM pressure and better vectorization efficiency.

As shown in Table 10, the RISC-V RV32IMAC platform exhibits an embedded-platform trade-off pattern similar to Cortex-M4. Compared with Sfull, Shalf reduces ROM from 2470 to 2242 B, while the cycle overhead remains moderate, increasing from 4180 to 4328 cycles per NTT. The energy overhead is also limited, increasing from 2.03 to 2.10µJ. These results indicate that the additional cost of branchless half-table reconstruction is relatively small compared with the ROM saving on a resource-constrained baseline core. In contrast, Sgen removes the twiddle table but significantly increases latency and energy consumption, reaching 7530 cycles and 3.65µJ per NTT. Therefore, on the tested RISC-V platform, on-the-fly generation is less attractive than Shalf for embedded deployment.

The x86-64 AVX2 platform shows a different trend. Although Shalf still reduces ROM compared with Sfull, the ROM saving is less important on a high-performance processor with a deeper memory hierarchy and stronger SIMD execution capability. On this platform, Sfull achieves the lowest latency and energy consumption, requiring only 890 cycles and 11.8µJ per NTT, whereas Shalf increases these values to 938 cycles and 12.5µJ. This platform-dependent reversal is important because it shows that the proposed framework does not always recommend the same strategy. Instead, the preferred implementation depends on the relative importance of ROM pressure, arithmetic overhead, and vectorization efficiency.

Table 11 further compares the MAT-predicted best strategy with the empirically observed best strategy. The prediction matches the empirical outcome on all three platforms. Specifically, Shalf is selected for ARM Cortex-M4 and RISC-V RV32IMAC because these platforms are more sensitive to ROM footprint and embedded-resource constraints. By contrast, Sfull is selected for x86-64 AVX2 because the platform benefits more from regular full-table access and vectorization-friendly data layout. This agreement supports the role of MAT as a hardware-aware strategy-selection framework rather than a single-device scoring rule. It also confirms that Shalf should be interpreted as a Pareto-efficient embedded compromise rather than a universal optimum across all platforms.

6.5 Timing-Trace and TVLA Results (STM32F407)

To support leakage-related claims with empirical evidence, we provide the results for timing traces and first-order TVLA on STM32F407. This subsection is intended to distinguish constant-time coding practice from a complete side-channel-security proof. The experiments evaluate whether the proposed branchless twiddle-factor reconstruction introduces observable timing distinguishability or first-order power leakage under the tested configuration.

We collected timing traces on STM32F407 for two datasets: fixed test vectors and random test vectors. Each dataset contains 20,000 samples. The mean cycle counts are 3226.23 for fixed vectors and 3226.24 for random vectors, with standard deviations of 1.94 and 1.97, respectively. A two-sample Welch’s t-test yields p=0.609, indicating no statistically significant evidence of timing distinguishability under this setup.

Table 12 shows that the mean cycle counts of the fixed-vector and random-vector groups are almost identical. The difference between the two means is only 0.01 cycles, which is much smaller than the observed standard deviations. This indicates that the tested branchless accessor does not introduce measurable timing variation between the two input classes in this experiment. The Welch’s t-test result further supports this observation, since p=0.609 does not indicate statistically significant timing distinguishability under the tested configuration.

For first-order TVLA, we compute Welch’s t-test between fixed and random groups over 5000 aligned power-trace points collected through the shunt-resistor measurement path. The maximum absolute statistic is |t|max=3.26. Using the standard threshold of |t| >4.5, the result is a pass for this experiment configuration, indicating no first-order leakage evidence under this setup for the branchless logic.

Table 13 reports the first-order TVLA result obtained from the shunt-resistor power-trace measurement path. The maximum absolute t-statistic is |t|max=3.26, which remains below the commonly used leakage-detection threshold of 4.5. This suggests that no first-order leakage evidence is observed for the tested branchless reconstruction logic under this experimental setup. However, this result should not be interpreted as a complete side-channel-security proof. Higher-order leakage, different probes, different compiler backends, electromagnetic measurements, and stronger adversarial models remain outside the current evaluation scope.

Taken together, Tables 12 and 13 indicate that the proposed branchless reconstruction logic does not show statistically significant timing distinguishability or first-order TVLA leakage evidence under the tested configuration, thereby supporting the claimed lower timing-risk profile of the proposed implementation.

7  Conclusion

This work presented a multi-dimensional analysis of twiddle-factor symmetry exploitation for ML-KEM. We formalized a branchless half-table reconstruction rule with implementation-consistent indexing, and we introduced a device-aware MAT framework with explicit security-risk cost semantics. Based on current evidence, we draw the following conclusions:

1.    On Cortex-M4, Shalf reduces twiddle-factor ROM by 50% with about 3%–6% cycle overhead in controlled C-level comparison, making it a strong embedded compromise.

2.    Under the MAT objective, Shalf is a Pareto-efficient knee point for ROM-constrained settings rather than a universal global optimum.

3.    MAT reproduces the Cortex-M4 ranking and remains robust under weight perturbation (98.3% of tested weight combinations select Shalf).

4.    The current revision distinguishes constant-time coding claims from full side-channel-security claims and provides cross-platform measurements (RISC-V and x86) together with empirical TVLA evidence supporting the security profile.

Future work will expand measurements to additional devices and higher-order leakage settings to further strengthen external validity.

Acknowledgement: Not applicable.

Funding Statement: The authors received no specific funding for this study.

Author Contributions: The authors confirm contribution to the paper as follows: Xiaobing Liang contributed to the study conception, algorithm design for Shalf strategy, formal analysis, and original draft preparation. Yu Qin contributed to the software implementation on ARM and RISC-V platforms, data curation, and assisted in the manuscript preparation. Shengdong Pan contributed to the construction and validation of the MAT model, visualization of experimental results, and participation in review and editing. Liang Tan supervised the overall research process, provided strategic guidance for multi-objective trade-off analysis, project administration, and secured key resources for the study. All authors reviewed and approved the final version of the manuscript.

Availability of Data and Materials: Not applicable.

Ethics Approval: Not applicable.

Conflicts of Interest: The authors declare no conflicts of interest.

Abbreviations

The following abbreviations are used in this manuscript:

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