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Read-Write Dependency Aware Register Allocation

Sheng Xiao1,*, Yong Chen2, Jing He3, Xi Yang4

1 School of Computer Science, Hunan First Normal University, Changsha, 410205, China
2 School of Information Engineering, Nanjing Audit University, Nanjing, 211815, China
3 Department of Computer Science, Kennesaw State University, Kennesaw, 30144-5588, USA
4 Hunan Huayi Experimental Middle School, Changsha, 410205, China

* Corresponding Author: Sheng Xiao. Email:

Computer Systems Science and Engineering 2023, 46(3), 3527-3540.


Read-write dependency is an important factor restricting software efficiency. Timing Speculative (TS) is a processing architecture aiming to improve energy efficiency of microprocessors. Timing error rate, influenced by the read-write dependency, bottlenecks the voltage down-scaling and so the energy efficiency of TS processors. We proposed a method called Read-Write Dependency Aware Register Allocation. It is based on the Read-Write Dependency aware Interference Graph (RWDIG) conception. Registers are reallocated to loosen the read-write dependencies, so resulting in a reduction of timing errors. The traditional no operation (Nop) padding method is also redesigned to increase the distance value to above 2. We analyzed the dependencies of registers and maximized the average distance value of read and write dependencies. Experimental results showed that we can reduce all read-write dependency by Nop padding, as well as the overhead timing errors. An energy saving of approximately 7% was achieved.


Cite This Article

S. Xiao, Y. Chen, J. He and X. Yang, "Read-write dependency aware register allocation," Computer Systems Science and Engineering, vol. 46, no.3, pp. 3527–3540, 2023.

This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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