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A Novel Workload-Aware and Optimized Write Cycles in NVRAM

J. P. Shri Tharanyaa1,*, D. Sharmila2, R. Saravana Kumar3
1 Department of ECE, Bannari Amman Institute of Technology, Tamil Nadu, India
2 Department of CSE, Jai Shriram Engineering College, Tamil Nadu, India
3 Department of ECE, Bannari Amman Institute of Technology, Tamil Nadu, India
* Corresponding Author: J. P. Shri Tharanyaa. Email:

Computers, Materials & Continua 2022, 71(2), 2667-2681.

Received 29 April 2021; Accepted 17 September 2021; Issue published 07 December 2021


With the emergence of the Internet of things (IoT), embedded systems have now changed its dimensionality and it is applied in various domains such as healthcare, home automation and mainly Industry 4.0. These Embedded IoT devices are mostly battery-driven. It has been analyzed that usage of Dynamic Random-Access Memory (DRAM) centered core memory is considered the most significant source of high energy utility in Embedded IoT devices. For achieving the low power consumption in these devices, Non-volatile memory (NVM) devices such as Parameter Random Access Memory (PRAM) and Spin-Transfer Torque Magnetic Random-Access Memory (STT-RAM) are becoming popular among main memory alternatives in embedded IoT devices because of their features such as high thickness, byte addressability, high scalability and low power intake. Additionally, Non-volatile Random-Access Memory (NVRAM) is widely adopted to save the data in the embedded IoT devices. NVM, flash memories have a limited lifetime, so it is mandatory to adopt intelligent optimization in managing the NVRAM-based embedded devices using an intelligent controller while considering the endurance issue. To address this challenge, the paper proposes a powerful, lightweight machine learning-based workload-adaptive write schemes of the NVRAM, which can increase the lifetime and reduce the energy consumption of the processors. The proposed system consists of three phases like Workload Characterization, Intelligent Compression and Memory Allocators. These phases are used for distributing the write-cycles to NVRAM, following the energy-time consumption and number of data bytes. The extensive experimentations are carried out using the IoMT (Internet of Medical things) benchmark in which the different endurance factors such as application delay, energy and write-time factors were evaluated and compared with the different existing algorithms.


Internet of things; DRAM; PRAM; STT-RAM; machine learning; internet of medical things; endurance

Cite This Article

J. P. Shri Tharanyaa, D. Sharmila and R. Saravana Kumar, "A novel workload-aware and optimized write cycles in nvram," Computers, Materials & Continua, vol. 71, no.2, pp. 2667–2681, 2022.

This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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