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High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

Ameen Bin Obadi1, Alaa El-Din Hussein2, Samir Salem Al-Bawri3,4,*, Kabir Hossain5, Abdullah Abdulhameed4, Muzammil Jusoh1,6,7, Thennarasan Sabapathy1,6, Ahmed Jamal Abdullah Al-Gburi8, Mahmoud A. Albreem9

1 Advanced Communication Engineering (ACE), Centre of Excellence, Universiti Malaysia Perlis (UniMAP), Faculty of Electronic Engineering Technology, Kangar, 01000, Malaysia
2 Electrical Engineering, King Fahd University of Petroleum and Minerals, Dhahran, Eastern, 31261, Saudi Arabia
3 Space Science Centre, Climate Change Institute, Universiti Kebangsaan Malaysia, Bangi, 43600, Malaysia
4 Department of Electronics & Communication Engineering, Faculty of Engineering & Petroleum, Hadhramout University, Al-Mukalla, Hadhramout, 50512, Yemen
5 Faculty of Engineering, Norwegian University of Science and Technology (NTNU), Gjøvik, N-2815, Norway
6 Faculty of Electronic Engineering Technology, Universiti Malaysia Perlis (UniMAP), Kampus Alam UniMAP Pauh Putra, Arau, 02600, Malaysia
7 Department of General Educational Development, Faculty of Science and Information Technology (FSIT), Daffodil International University, Dhaka, 1207, Bangladesh
8 Department of Electronics and Computer Engineering (FKEKK), Center for Telecommunication Research and Innovation (CeTRI), Universiti Teknikal Malaysia Melaka (UTeM), Durian Tungal, 76100, Malaysia
9 Department of Electrical Engineering, University of Sharjah, Sharjah, 27272, United Arab Emirates

* Corresponding Author: Samir Salem Al-Bawri. Email: email

Computers, Materials & Continua 2023, 74(3), 5885-5900. https://doi.org/10.32604/cmc.2023.033789

Abstract

This article presents an integrated current mode configurable analog block (CAB) system for field-programmable analog array (FPAA). The proposed architecture is based on the complementary metal-oxide semiconductor (CMOS) transistor level design where MOSFET transistors operating in the saturation region are adopted. The proposed CAB architecture is designed to implement six of the widely used current mode operations in analog processing systems: addition, subtraction, integration, multiplication, division, and pass operation. The functionality of the proposed CAB is demonstrated through these six operations, where each operation is chosen based on the user’s selection in the CAB interface system. The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations. Furthermore, optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells. Moreover, these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design. Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35 μm standard CMOS technology. The design uses a  V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 . This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article. Consequently, the proposed design has a clear aspect of simplicity, low power consumption, and high bandwidth operation, which makes it a suitable candidate for mobile telecommunications applications.

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APA Style
Obadi, A.B., Hussein, A.E., Al-Bawri, S.S., Hossain, K., Abdulhameed, A. et al. (2023). High-bandwidth, low-power CMOS transistor based CAB for field programmable analog array. Computers, Materials & Continua, 74(3), 5885-5900. https://doi.org/10.32604/cmc.2023.033789
Vancouver Style
Obadi AB, Hussein AE, Al-Bawri SS, Hossain K, Abdulhameed A, Jusoh M, et al. High-bandwidth, low-power CMOS transistor based CAB for field programmable analog array. Comput Mater Contin. 2023;74(3):5885-5900 https://doi.org/10.32604/cmc.2023.033789
IEEE Style
A.B. Obadi et al., "High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array," Comput. Mater. Contin., vol. 74, no. 3, pp. 5885-5900. 2023. https://doi.org/10.32604/cmc.2023.033789



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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