Open Access

ARTICLE

BFROU: A Reconfigurable Operation Unit Design Approach Using NPN Equivalence and Reed-Muller Logic Unit for Boolean Functions in Stream Ciphers

Zhaoxu Zhou, Yanjiang Liu, Zibin Dai^*, Junwei Li

Information Engineering University, Zhengzhou, China

* Corresponding Author: Zibin Dai. Email:

Computers, Materials & Continua 2026, 88(2), 30 https://doi.org/10.32604/cmc.2026.080072

Received 02 February 2026; Accepted 25 March 2026; Issue published 15 June 2026

Abstract

Stream ciphers are simple to implement and fast at encrypting and decrypting data, making them very important in information security. Boolean functions are a core part of stream ciphers. However, their mainstream hardware implementations face two main problems, including wasted area resources and excessive critical path delay. These issues limit the energy efficiency and integration level of stream cipher chips. To address these problems, this paper proposes an energy-efficient design method for a 64-bit Boolean function reconfigurable operation unit (BFROU), aiming to improve the computational efficiency of Boolean functions in stream ciphers. To optimize the design of BFROU, this paper takes the NPN equivalence theory as a guide. First, customized designs at the transistor level were performed for both 2- and 3-variable RM logic units (denoted as TRM). On this basis, this paper uses the port sharing strategy to further optimize the design of 4-to-6-variable TRM logic units and construct a multi-variable TRM process library. Then, by combining multi-variable TRM logic units with the mathematical definition of Boolean functions, this paper proposes a theoretical model of BFROU. Based on this model and combined with the statistical analysis results of Boolean functions, the optimal TRM unit configuration is determined, and the overall optimization of the 64-bit BFROU is finally completed. Experimental results show that when TRM-3 and TRM-4 units are mixed as the first-level operation module of BFROU, its area-delay product (ADP) reaches the minimum. The 64-bit BFROU unit implemented according to this scheme has an actual measured area of 137.28 μm² and a critical path delay of 0.278 ns under the SMIC 40 nm typical process corner. This unit supports Boolean function operations with up to 64 variables, and 94.4% of the functions can complete mapping within 2 iterations. Compared with existing schemes such as look-up table (LUT) architecture and And-Inverter Cone (AIC) array, the BFROU proposed in this paper has obvious advantages in area, delay, ADP and number of iterations, providing effective hardware support for the design of high-energy-efficiency stream cipher chips.

---

Keywords

---