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Smart Communication Using 2D and 3D Mesh Network-on-Chip

Arpit Jain1,*, Adesh Kumar2, Anand Prakash Shukla3, Hammam Alshazly4, Hela Elmannai5, Abeer D. Algarni5, Roushan Kumar6, Jitendra Yadav6

1 Department of Computer Science, Teerthanker Mahaveer University, Moradabad, India
2 Department of Electrical & Electronics Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India
3 Government Polytechnic, Bijnor, 246276, Uttar Pradesh, India
4 Faculty of Computers and Information, South Valley University, Qena, 83523, Egypt
5 Department of Information Technology, College of Computer and Information Sciences, Princess Nourah bint Abdulrahman University, P.O.Box 84428, Riyadh 11671, Saudi Arabia
6 Department of Mechanical Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India

* Corresponding Author: Arpit Jain. Email: email

Intelligent Automation & Soft Computing 2022, 34(3), 2007-2021. https://doi.org/10.32604/iasc.2022.024770

Abstract

Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D and 3D mesh NoC respectively. The functional simulation is performed on Modelsim 10.0 software. The on-chip communicationis verified for 2D and 3D mesh NoC with different cluster sizes that pre-estimates the hardware resources utilization on FPGA. The algorithm provides a substantial platform to NoC designers to overcome the issues of substantial configuration in NoC synthesis on FPGA in case of multiple processing elements, routers, cache controllers are integrated with SoC. The suggested NoC is helpful for the embedded system design of smart wireless communication.

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APA Style
Jain, A., Kumar, A., Shukla, A.P., Alshazly, H., Elmannai, H. et al. (2022). Smart communication using 2D and 3D mesh network-on-chip. Intelligent Automation & Soft Computing, 34(3), 2007-2021. https://doi.org/10.32604/iasc.2022.024770
Vancouver Style
Jain A, Kumar A, Shukla AP, Alshazly H, Elmannai H, Algarni AD, et al. Smart communication using 2D and 3D mesh network-on-chip. Intell Automat Soft Comput . 2022;34(3):2007-2021 https://doi.org/10.32604/iasc.2022.024770
IEEE Style
A. Jain et al., "Smart Communication Using 2D and 3D Mesh Network-on-Chip," Intell. Automat. Soft Comput. , vol. 34, no. 3, pp. 2007-2021. 2022. https://doi.org/10.32604/iasc.2022.024770



cc Copyright © 2022 The Author(s). Published by Tech Science Press.
This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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