K. N. Vijeyakumar1, S. Maragatharaj2,*
CMC-Computers, Materials & Continua, Vol.70, No.2, pp. 2543-2561, 2022, DOI:10.32604/cmc.2022.019789
Abstract Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications. This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry (PC) generation logic. For ‘n’ bits in input, the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits. A simple OR logic with no carry propagation is used to implement the approximate part. In the exact part, addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical… More >
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