Nagarajan Shanmugam^*, Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram, Saravanakumar Natarajan

Computer Systems Science and Engineering, Vol.42, No.2, pp. 619-638, 2022, DOI:10.32604/csse.2022.021008

Abstract In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the proposed compression idealogy are more… More >

V. Magesh^1,*, N. Duraipandian²

Intelligent Automation & Soft Computing, Vol.31, No.3, pp. 1499-1510, 2022, DOI:10.32604/iasc.2022.020552

Abstract The current research paper discusses the implementation of higher order-matched filter design using odd and even phase processes for efficient area and time delay reduction. Matched filters are widely used tools in the recognition of specified task. When higher order taps are implemented upon the transposed form of matched filters, it can enhance the image recognition application and its performance in terms of identification and accuracy. The proposed method i.e., odd and even phases’ process of FIR filter can reduce the number of multipliers and adders, used in existing system. The main advantage of using higher order tap-matched filter is… More >