R. Agalya1, R. Muthaiah2,*, D. Muralidharan3
CMES-Computer Modeling in Engineering & Sciences, Vol.120, No.1, pp. 25-43, 2019, DOI:10.32604/cmes.2019.05616
Abstract In today’s modern design technology, post-silicon validation is an expensive and composite task. The major challenge involved in this method is that it has limited observability and controllability of internal signals. There will be an issue during execution how to address the useful set of signals and store it in the on-chip trace buffer. The existing approaches are restricted to particular debug set-up where all the components have equivalent prominence at all the time. Practically, the verification engineers will emphasis only on useful functional regions or components. Due to some constraints like clock gating, some of the regions can be… More >
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