S. Senthilmurugan1,*, K. Gunaseelan2
Intelligent Automation & Soft Computing, Vol.35, No.2, pp. 1323-1336, 2023, DOI:10.32604/iasc.2023.027650
Abstract A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits (ICs) fabrication industries. Because whenever device size comes down into narrow, designers facing many power density issues should be reduced by scaling threshold voltage and supply voltage. Initially, Complementary Metal Oxide Semiconductor (CMOS) technology supports power saving up to 32 nm gate length, but further scaling causes short severe channel effects such as threshold voltage swing, mobility degradation, and more leakage power (less than 32) at gate length. Hence, it directly affects the arithmetic logic unit (ALU), which suffers a significant power… More >
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