Turki M. Alanazi, Ahmed Ben Atitallah*
CMC-Computers, Materials & Continua, Vol.71, No.3, pp. 4319-4335, 2022, DOI:10.32604/cmc.2022.022988
Abstract As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for… More >
Login
Register
