Praveena R1, *
CMC-Computers, Materials & Continua, Vol.63, No.1, pp. 85-95, 2020, DOI:10.32604/cmc.2020.08629
- 30 March 2020
Abstract Digital design of a digital signal processor involves accurate and high-speed mathematical computation units. DSP units are one of the most power consuming and memory occupying devices. Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices. This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit. A lookup table-based multiplier has the advantage of almost constant area requirement’s irrespective to the increase in bit size of multiplier. Clock gating More >
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