Hojin Kang1, Syed Asmat Ali Shah2, HyungWon Kim1,*
CMC-Computers, Materials & Continua, Vol.72, No.1, pp. 2127-2139, 2022, DOI:10.32604/cmc.2022.025798
Abstract This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.… More >
Login
Register
