P. PattunnaRajam1, *, Reeba korah2, G. Maria Kalavathy3
CMC-Computers, Materials & Continua, Vol.54, No.3, pp. 251-268, 2018, DOI:10.3970/cmc.2018.054.251
Abstract This paper presents an automated POCOFAN-POFRAME algorithm that partitions large combinational digital VLSI circuits for pseudo exhaustive testing. In this paper, a simulation framework and partitioning technique are presented to guide VLSI circuits to work under with fewer test vectors in order to reduce testing time and to develop VLSI circuit designs. This framework utilizes two methods of partitioning Primary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning to determine number of test vectors in the circuit. The key role of partitioning is to identify reconvergent fanout branch pairs and the optimal value of primary input node N and fanout… More >
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