Liangbo Xie1, Yan Ren1, Mu Zhou1, Xiaolong Yang1,*, Zhengwen Huang2
CMC-Computers, Materials & Continua, Vol.69, No.2, pp. 1597-1609, 2021, DOI:10.32604/cmc.2021.018502
Abstract This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The time-domain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator… More >
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