Babangida Isyaku^1,2,*, Kamalrulnizam Bin Abu Bakar¹, Wamda Nagmeldin³, Abdelzahir Abdelmaboud⁴, Faisal Saeed^5,6, Fuad A. Ghaleb¹

Computer Systems Science and Engineering, Vol.46, No.3, pp. 3729-3748, 2023, DOI:10.32604/csse.2023.034509

Abstract Software Defined Networks (SDN) introduced better network management by decoupling control and data plane. However, communication reliability is the desired property in computer networks. The frequency of communication link failure degrades network performance, and service disruptions are likely to occur. Emerging network applications, such as delay-sensitive applications, suffer packet loss with higher Round Trip Time (RTT). Several failure recovery schemes have been proposed to address link failure recovery issues in SDN. However, these schemes have various weaknesses, which may not always guarantee service availability. Communication paths differ in their roles; some paths are critical because of the higher frequency usage.… More >

A. P. Chassiakos, C. I. Samaras, D. D. Theodorakopoulos¹

CMES-Computer Modeling in Engineering & Sciences, Vol.1, No.4, pp. 9-18, 2000, DOI:10.3970/cmes.2000.001.461

Abstract Time and cost to complete a project is an important tradeoff problem in project planning and control. Existing methods have not provided an accepted solution in terms of both accuracy and efficiency. In an attempt to improve the solution process, a method is presented for developing optimal project time-cost curves based on CPM analysis. Using activity succession information, project paths are developed and duration is calculated. Following that, duration is reduced in an optimal way employing integer programming. Two alternative formulations are proposed which lead to corresponding algorithms, a progressive duration reduction and a direct reduction to the desired level.… More >

P. PattunnaRajam^{1, *}, Reeba korah², G. Maria Kalavathy³

CMC-Computers, Materials & Continua, Vol.54, No.3, pp. 251-268, 2018, DOI:10.3970/cmc.2018.054.251

Abstract This paper presents an automated POCOFAN-POFRAME algorithm that partitions large combinational digital VLSI circuits for pseudo exhaustive testing. In this paper, a simulation framework and partitioning technique are presented to guide VLSI circuits to work under with fewer test vectors in order to reduce testing time and to develop VLSI circuit designs. This framework utilizes two methods of partitioning Primary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning to determine number of test vectors in the circuit. The key role of partitioning is to identify reconvergent fanout branch pairs and the optimal value of primary input node N and fanout… More >