Zicheng Zhou¹, Shaowen Sun², Teng Liang³, Mengjuan Li^4,*, Fengling Xia^5,*

CMC-Computers, Materials & Continua, Vol.82, No.1, pp. 1313-1327, 2025, DOI:10.32604/cmc.2024.056880 - 03 January 2025

Abstract Z-curve’s encoding and decoding algorithms are primely important in many Z-curve-based applications. The bit interleaving algorithm is the current state-of-the-art algorithm for encoding and decoding Z-curve. Although simple, its efficiency is hindered by the step-by-step coordinate shifting and bitwise operations. To tackle this problem, we first propose the efficient encoding algorithm LTFe and the corresponding decoding algorithm LTFd, which adopt two optimization methods to boost the algorithm’s efficiency: 1) we design efficient lookup tables (LT) that convert encoding and decoding operations into table-lookup operations; 2) we design a bit detection mechanism that skips partial order More >

S. Nithya Devi^1,*, S. Sasipriya²

Computer Systems Science and Engineering, Vol.43, No.2, pp. 423-437, 2022, DOI:10.32604/csse.2022.022280 - 20 April 2022

Abstract In real-time applications, unpredictable random numbers play a major role in providing cryptographic and encryption processes. Most of the existing random number generators are embedded with the complex nature of an amplifier, ring oscillators, or comparators. Hence, this research focused more on implementing a Hybrid Nature of a New Random Number Generator. The key objective of the proposed methodology relies on the utilization of True random number generators. The randomness is unpredictable. The additions of programmable delay lines will reduce the processing time and maintain the quality of randomizing. The performance comparisons are carried out More >

Praveena R^{1, *}

CMC-Computers, Materials & Continua, Vol.63, No.1, pp. 85-95, 2020, DOI:10.32604/cmc.2020.08629 - 30 March 2020

Abstract Digital design of a digital signal processor involves accurate and high-speed mathematical computation units. DSP units are one of the most power consuming and memory occupying devices. Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices. This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit. A lookup table-based multiplier has the advantage of almost constant area requirement’s irrespective to the increase in bit size of multiplier. Clock gating More >