Muhammad Ali, Minhaj Ahmad Khan^*

Computer Systems Science and Engineering, Vol.48, No.2, pp. 287-303, 2024, DOI:10.32604/csse.2023.043010

Abstract The Extensible Markup Language (XML) files, widely used for storing and exchanging information on the web require efficient parsing mechanisms to improve the performance of the applications. With the existing Document Object Model (DOM) based parsing, the performance degrades due to sequential processing and large memory requirements, thereby requiring an efficient XML parser to mitigate these issues. In this paper, we propose a Parallel XML Tree Generator (PXTG) algorithm for accelerating the parsing of XML files and a Regression-based XML Parsing Framework (RXPF) that analyzes and predicts performance through profiling, regression, and code generation for efficient parsing. The PXTG algorithm… More >

Allam Abumwais^*, Mujahed Eleyat

CMC-Computers, Materials & Continua, Vol.77, No.1, pp. 615-632, 2023, DOI:10.32604/cmc.2023.038810

Abstract Recent architectures of multi-core systems may have a relatively large number of cores that typically ranges from tens to hundreds; therefore called many-core systems. Such systems require an efficient interconnection network that tries to address two major problems. First, the overhead of power and area cost and its effect on scalability. Second, high access latency is caused by multiple cores’ simultaneous accesses of the same shared module. This paper presents an interconnection scheme called N-conjugate Shuffle Clusters (NCSC) based on multi-core multi-cluster architecture to reduce the overhead of the just mentioned problems. NCSC eliminated the need for router devices and… More >

Allam Abumwais^*, Mahmoud Obaid

CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 4951-4963, 2023, DOI:10.32604/cmc.2023.032822

Abstract Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used… More >

J. Jean Justus¹, U. Sakthi², K. Priyadarshini³, B. Thiyaneswaran⁴, Masoud Alajmi⁵, Marwa Obayya⁶, Manar Ahmed Hamza^7,*

Computer Systems Science and Engineering, Vol.44, No.1, pp. 205-219, 2023, DOI:10.32604/csse.2023.025256

Abstract The developments of multi-core systems (MCS) have considerably improved the existing technologies in the field of computer architecture. The MCS comprises several processors that are heterogeneous for resource capacities, working environments, topologies, and so on. The existing multi-core technology unlocks additional research opportunities for energy minimization by the use of effective task scheduling. At the same time, the task scheduling process is yet to be explored in the multi-core systems. This paper presents a new hybrid genetic algorithm (GA) with a krill herd (KH) based energy-efficient scheduling technique for multi-core systems (GAKH-SMCS). The goal of the GAKH-SMCS technique is to… More >

Ke Song^1,*, Paul Liu², Dongquan Liu³

CMES-Computer Modeling in Engineering & Sciences, Vol.128, No.3, pp. 1133-1150, 2021, DOI:10.32604/cmes.2021.016008

Abstract A novel beamforming algorithm named Delay Multiply and Sum (DMAS), which excels at enhancing the resolution and contrast of ultrasonic image, has recently been proposed. However, there are nested loops in this algorithm, so the calculation complexity is higher compared to the Delay and Sum (DAS) beamformer which is widely used in industry. Thus, we proposed a simple vector-based method to lower its complexity. The key point is to transform the nested loops into several vector operations, which can be efficiently implemented on many parallel platforms, such as Graphics Processing Units (GPUs), and multi-core Central Processing Units (CPUs). Consequently, we… More >