K. Chanthirasekaran, Raghu Gundaala*
Intelligent Automation & Soft Computing, Vol.37, No.1, pp. 471-489, 2023, DOI:10.32604/iasc.2023.036130
Abstract When it comes to decreasing margins and increasing energy efficiency in near-threshold and sub-threshold processors, timing error resilience may be viewed as a potentially lucrative alternative to examine. On the other hand, the currently employed approaches have certain restrictions, including high levels of design complexity, severe time constraints on error consolidation and propagation, and uncontaminated architectural registers (ARs). The design of near-threshold circuits, often known as NT circuits, is becoming the approach of choice for the construction of energy-efficient digital circuits. As a result of the exponentially decreased driving current, there was a reduction in performance, which was one of… More >
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