Liangbo Xie¹, Yan Ren¹, Mu Zhou¹, Xiaolong Yang^1,*, Zhengwen Huang²

CMC-Computers, Materials & Continua, Vol.69, No.2, pp. 1597-1609, 2021, DOI:10.32604/cmc.2021.018502

Abstract This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The time-domain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator… More >

Liangbo Xie^{1, *}, Sheng Li¹, Yan Ren¹, Zhengwen Huang²

CMC-Computers, Materials & Continua, Vol.65, No.2, pp. 1519-1529, 2020, DOI:10.32604/cmc.2020.011701

Abstract This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register (SAR) analog-to-digital converters (ADCs). The proposed two-dimension time-domain comparator consists of a ring oscillator collapsebased comparator and a counter. The propagation delay of a voltage controlled ring oscillator depends on the input. Thus, the comparator can automatically change the comparison time according to its input difference, which can adjust the power consumption of the comparator dynamically without any control logic. And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small. Thus, the proposed comparator can not only… More >