M. Geetha^1,*, R. Vijayabhasker², Suresh Seetharaman¹

Computer Systems Science and Engineering, Vol.44, No.1, pp. 813-832, 2023, DOI:10.32604/csse.2023.025575

Abstract A basic 7-level MLI topology is developed and the same is extended to the 9-level then further increased to 17-levels. The developed structure minimizes the component’s count and size to draw out the system economy. Despite the various advantages of MLIs, efficiency and reliability play a major role since the usage of components is higher for getting a low Total Harmonics Distortion (THD) value. This becomes a major challenge incorporated in boosting the efficiency without affecting the THD value. Various parametric observations are done and realized for the designed 9-level and 17-level MLI, being the Total Standing Voltage (TSV), efficiency,… More >

Hojin Kang¹, Syed Asmat Ali Shah², HyungWon Kim^1,*

CMC-Computers, Materials & Continua, Vol.72, No.1, pp. 2127-2139, 2022, DOI:10.32604/cmc.2022.025798

Abstract This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.… More >