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An Efficient AES 32-Bit Architecture Resistant to Fault Attacks

Hassen Mestiri1,2,3,*, Imen Barraj4,5, Abdullah Alsir Mohamed1, Mohsen Machhout3

1 Department of Computer Engineering, College of Computer Engineering and Sciences, Prince Sattam bin Abdulaziz University, Al-Kharj, 11942, Saudi Arabia
2 Higher Institute of Applied Sciences and Technology of Sousse, University of Sousse, Tunisia
3 Electronics and Micro-Electronics Laboratory, Faculty of Sciences of Monastir, University of Monastir, Tunisia
4 METS Research Group, Electrical Engineering Department, National Engineers School of Sfax, University of Sfax, Tunisia
5 Higher Institute of Computer Science and Multimedia of Gabes, University of Gabes, Tunisia

* Corresponding Author: Hassen Mestiri. Email: email

Computers, Materials & Continua 2022, 70(2), 3667-3683.


The Advanced Encryption Standard cryptographic algorithm, named AES, is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange. One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data. Until now, a several AES fault detection schemes against fault injection attacks have been proposed. In this paper, so as to ensure a high level of security against fault injection attacks, a new efficient fault detection scheme based on the AES architecture modification has been proposed. For this reason, the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them. The proposed scheme is independent of the procedure the AES is implemented. Thus, it can be implemented to secure the pipeline and iterative architectures. To evaluate the robustness of the proposed fault detection scheme against fault injection attacks, we conduct a transient and permanent fault attacks and then we determine the fault detection capability; it is about 99.88585% and 99.9069% for transient and permanent faults respectively. We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation. The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme.


Cite This Article

APA Style
Mestiri, H., Barraj, I., Mohamed, A.A., Machhout, M. (2022). An efficient AES 32-bit architecture resistant to fault attacks. Computers, Materials & Continua, 70(2), 3667-3683.
Vancouver Style
Mestiri H, Barraj I, Mohamed AA, Machhout M. An efficient AES 32-bit architecture resistant to fault attacks. Comput Mater Contin. 2022;70(2):3667-3683
IEEE Style
H. Mestiri, I. Barraj, A.A. Mohamed, and M. Machhout "An Efficient AES 32-Bit Architecture Resistant to Fault Attacks," Comput. Mater. Contin., vol. 70, no. 2, pp. 3667-3683. 2022.


cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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