Open Access

ARTICLE

Performance Analysis of AODV Routing for Wireless Sensor Network in FPGA Hardware

Namit Gupta^1,*, Kunwar Singh Vaisla², Arpit Jain³, Adesh Kumar⁴, Rajeev Kumar³

1 Department of Computer Science & Engineering, Uttarakhand Technical University, Dehradun, 248007, India
2 Department of Computer Science, B T Kumaon Institute of Technology Dwarahat, India
3 Faculty of Engineering & CS, Teerthanker Mahaveer University, Moradabad, India
4 Department of Electrical & Electronics Engineering, School of Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India

* Corresponding Author: Namit Gupta. Email:

(This article belongs to the Special Issue: Emerging Trends in Intelligent Communication and Wireless Technologies)

Computer Systems Science and Engineering 2022, 40(3), 1073-1084. https://doi.org/10.32604/csse.2022.019911

Received 01 May 2021; Accepted 03 June 2021; Issue published 24 September 2021

Abstract

Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip is studied based on the field-programmable gate array (FPGA) hardware parameters such as slices, lookup table (LUTs), input/output block (IOB), flip-flops, and memory for the different configurations of the network (N = 10, 20 ….100). The delay and frequency are also estimated on the Virtex-5 FPGA. The performance of the WSN with AODV routing is also analyzed based on the packet delivery ratio, throughput, delay, and control overhead. The simulation test cases verified the 8-bit, 64-bit, and 128-bit data communication within the nodes.

---

Keywords

---