Ring Oscillator for 60 Meter Bandwidth

Nomenclature

1  Introduction

The significance of ring oscillator within the electronic commerce is conclusive. Through the massive enlargement in VLSI field, their values excessively increased. Each and every recent communication structure needs a steady cyclic signal for sampling, organizing and for frequency synthesis. The generation of clock is provided by the integrated on chop oscillator. The voltage control oscillator design faces numerous challenges similar to; achieve extensive tuning range, reduction in size (difficult to get technological features), stimulate on low supply and uphold the adequate power expenditure. The voltage oscillators can be categorizing into two major categories; Ring type and LC type oscillator. The LC type has some features like superior phase noise, excellent frequency performance, as these have high quality factor. The center frequency is highly dependent on inductor and capacitors. The characteristics impedance of this oscillator is directly proportional to inductor values [1,2]. To balance the series resistance losses, a parallel resistance is also coupled to sustain the oscillations therefore, the power consumption is increased. To maintain the circuit complexity, induction of eddy currents, oversized layout area, resultant resonant frequencies are exceptionally difficult task. Alternatively, ample frequency range as well as low power expenditure is easily achieved via ring oscillator architecture. The analogue to digital circuits, phase lock loops, and voltage control oscillators have remarkable handling of these ring oscillators. These oscillators engage fewer chip area so it has better chip density. Nevertheless, it has some foremost issues as frequency restrictions, number of stages used along with the each one inverter’s delay time. The projected designed uses 45 nm CMOS tool and achieve utmost frequency of 5.2 MHz with extremely low power expenditure of 1.852 μW.

The block plan of Ring Oscillators is shown in Fig. 1. It has three-inverter stage connected in series and some part of the throughput is feedback to the input to maintain the oscillations. Ideal RO contains, loop of “n” inverter stage, connected back to back to provide the oscillated output. The primarily use of RO is in favour of VCO (Voltage Control Oscillator), conceivably the most significant block of PLL (Phase Lock Loop). It will used to manage the mid-range frequency and bandwidth. The tuning range will follow the alteration in centre frequency. As the gain of the VCO changed, non-linearity in tuning range will occur. The essential function of VCO is to achieve constant oscillation therefore the generated voltage will maintain the lock condition. Yet a constant error voltage is the input of VCO, its output is not ideally periodic. Mainly all the electronic devices suffer with supply noise that added to the output and causes jitter [3,4].

Figure 1: Three stage single ended ring oscillator

By using odd numbers of inverters, the circuit cannot have fixed operating point. As a result the output should be oscillating in nature with satisfying the gain of a close loop system (larger than 1); the initial standard is met. Toward the second standard (achieve a phase shift of 180°), minimum 3-holdup cell are requisite [5,6]. The propagation delay is shown in the Fig. 2. The fastest oscillation can be achieved by three inverter stages. It is identified; the number of stages will enhance the power expenditure, so the planned RO is calculatingly planned by least delay stages. Fractional positive feedback is also recommended to diminish the power consumption. For the fundamental principle of three stage RO, let us assume the first NOT gate output is achieved by time t1 voltage switch to logic “1”. As soon as, logic “1” propagates to the closing stage, it produces logic “1” to the third stage. This is again feedback to the input and generates logic “0” to the first inverter output. Once this logic “0”, propagated to the loop, it will toggle the output of the 1st stage. For each rotation, an up and down transition will take place. The delay time of each stage is calculated by high-to-low (tPHL) and low-to-high (tHPL) transitions [7]. Yet, both times are not equal as a result the average propagation delay (tPHL + tHPL)/2 can be valid. The whole oscillation period is calculated as T = 2ntd and frequency of oscillation is fo=12ntd , where: T is the total time period of the circuit, td is total circuit delay. Three stage ring oscillator T = 6td and f0 = 1/6 td. As a result, via reducing the number of delay cells, the oscillation frequency enhances and delay time reduces. To manipulate the performance of RO, numerous methods are used like varying the load, varying the power of inverter and with changeable supply voltage [8]. This oscillator uses PMOS as pull up transistor or load because obscurity of implement the R and C in CMOS technology and NMOS is use like control transistor. The transfer function H (jω) of 3-stage ring oscillator is expressed by Eq. (1).

H(jω)=(−gmR1+jωRC)3 (1)

To fulfill the Barkhausen’s criteria, the phase shift of total circuit is equal to 180°. Therefore, for this oscillator, all the stages must contribute 60° phase shift. The magnitude of gain @ oscillation frequency should be ≥ 1. Thus,

tan−1(ωoRC)=60∘ (2)

(gmR)3(1+(ωoRC)2)32 ≥1 (3)

So the gain of every stage must be greater or equal to 2 ( gmR≥2 ). Therefore, this circuit is an astable type oscillator circuit. Where; gm is the trans-conductance of CMOS transistor and ωo is the angular frequency of oscillator.

Figure 2: Output response of ring oscillator

As describe by the Fig. 2 A, B and C are the clock, input and output waves are shown respectively. The delay of input and output throughput is shown. For all the inverter circuit the fan-out is one [9,10]. The main benefit of ring oscillator is the designing of circuit: with transistor designing, it uses very less area so the power density is very low. This oscillator is easy to tune so it provides wide bandwidth. The major problem with this oscillator is poor phase noise. As a result, this is mainly used for clock recovery, generation, and synchronization. As odd numbers of inverter stages are used to the circuit it do not have constant quiescent point so it and oscillate [11]. The primary motive for CMOS oscillator is to use for high frequencies, low power expenditure plus superior phase noise rather than other VCO designs. The fine-tuning of ring oscillator is lying on the supply voltage as well as the length of transistor’s channel. Conversely, the supply effect is less as compared to the channel width and length of transistor, however the realistic constraints limits these parameter to an optimum range [12]. In the Section 2, the basic delay cell is discussed with switched diagram. Section 3, represents the performance of ring oscillator with fixed capacitor. In Section 4, the variable sweep capacitor is used with ring oscillator and simulation consequences are presented. In Section 5, the result analysis is discussed and in the Section 6, the conclusion is made based on circuit analysis.

2  The Static CMOS Inverter

CMOS based inverter circuit is used as delay cell to form the ring oscillator. The odd numbers of inverters are connected in series to provide oscillations to the circuit. For the designing of ring oscillator, three conjugative stages are used for the proposed design.

Fig. 3 shows a ring oscillator inverter cell. This is using two transistors (PMOS and NMOS) in a cascaded manner. When the input is high, it will provide the low output and vice versa. For 45 nm, CMOS technology the charge carrier mobility of NMOS is 2.5 times of PMOS mobility. So aspect ratio of 2.66 is selected for PMOS and NMOS [13,14] transistors.

Figure 3: CMOS implementation of NOT gate (delay cell)

The Fig. 4 shows the input and output waveforms of CMOS inverter. The propagation delay of inverter is dependent on the time constant of the projected circuit. The time constant is dependent on the pull down resistor and the load capacitor values [15]. The schematic diagram of inverter with load capacitor is shown in Fig. 5. The switch analysis is subjected by the capacitance connected at the output (CL) that is tranquil of diffusion capacitances (Drain) of NMOS and PMOS transistors, wire capacitances plus i/p capacitance of gates connected at load (Eq. (6)). Let us assume, for low to high changeover, the PMOS is working as static switch. The response time of gate is the time; take to charge CL via PMOS internal resistance Rp. So the propagation delay (tpLH) of the circuit is proportional to the time constant RpCL [16]. Therefore, a rapid gate is built; whichever via choosing the low output capacitance or else through decrease the PMOS resistance.

Figure 4: Simulated I/P and O/P waveforms of inverter

Figure 5: The switched diagram of inverter with load capacitor

The second one can be achieved via increasing the W/L (Aspect Ratio) of the transistor. The analogous conditions are applicable for high to low transition time delay (tPHL), dominated by RnCL. As the turn on resistance of both transistors are not constant, although having a nonlinear role of voltage applied across the transistor. This complicates the precise calculation of overall propagation delay. So by taking the average of high to low and low to high transition we get, tp=tPHL+tPLH2=0.69CLRn+RP2 , If the rise and fall time should be equal than Rn = Rp. The time at 50% waveform point is t = 0.69RnCL. The time at 90% waveform point is t = 2.2 Rn CL. The overall load capacitor is the combination of all the capacitances as represented by Eq. (4).

CL=Cinternal+Cexternal+Cwire (4)

CL=CoxWpLp+CoxWnLn  (5)

Internal resistance of NMOS (Rn)=LnWnkn(VDD−VT) (6)

Internal resistance of PMOS Rp=LpWpkp(VDD−VT) (7)

where: Wn is the width of the p transistors and Wn is the width of n type transistor, Ln & Lp are the length of n type and p type transistor, Cox is capacitor density of gate oxide (25 fF/ μm2), Kn & Kp are the trans-conductance of p type and n type transistor, Rn & Rp is the internal resistance of n type and p type transistor, VT is threshold voltage (-0.22 V for PMOS and 0.22 V for NMOS) [17]. In view of the fact that every facet positioned to the pathway, create some leakage value of resistance to the ground, and this will reduces the overall gain of the system. By escalating the feedback path resistor, its outcome can also be minimized and the oscillating frequency is minimized, as they are inversely proportional to each other [18]. This type of arrangement is only worn for rapidity modeling. Furthermore, to fulfill the Barkhausen criteria some amount of noise is also needed. Intrinsic amount of noise is amplified to the high gain and provides sustained oscillations. In view of the fact, that the power utilization is subsequently important for designing of any oscillator. The configuration of ring oscillator consists of a source with the same gain stages to produce periodic waveforms by a set frequency [19]. The frequency is controlled by adjusting the delay of the gain stage. This is capable by varying the available current toward the charging of the load capacitor of the circuit. The overall power debauchery can be separated in two parts. The first one is the power consumed by the current source and another is by the overall circuit. The totality of power dissipation is PTotal = VDD Ic = VDD (n CLVc f0). At the similar time, power degenerate by the inverters is P = Vc Ic = N CLVc2f0 .The dissipated power (Pcs) by current source is Pcs = PTotal-P = VDD (N CLVc f0)–N CLVc2f0. Where, Vc is average energy across the inverter, Ic is the current flowing through the load capacitor, fo is the frequency of oscillation of the circuit. For low power systems, it is essential to diminish power expenditure [20,21]. The overall power expenditure is related to number of stages used to the circuit and the related load capacitor. By minimizing the voltage across capacitor, the power loss by the inverter cell is also reduced. In addition, this will result to diminish the phase noise of the circuit. A midway has to be finding for good performance of the circuit.

3  Three Stage Oscillator with Fixed Capacitor

This circuit is having three inverter positioned in cascading. An uncomplicated three-stage ring oscillator is shown in Fig. 6. As high digital signal is applying to the input of first inverter, it propagates to the cell and low signal is delivered to the output. Again, this signal is fed back towards the input terminal and again this succession is started. As for the inverter circuit, as low signal is apply to the inverter input, the PMOS is turned on and NMOS is turned off so it will produce high signal at output. This high signal is fed to the next stage input terminal. This will switch off the PMOS and switch on the NMOS, consequently produce a low signal [22,23]. For suitable operation of ring oscillator, it requires odd numbers of NOT gates. The oscillating frequency can be calculated by the following equation Eq. (8).

 tPHL+tPLH=1(2n+1)frequency (8)

Figure 6: Simulated model of cmos based ring oscillator with 45 nm technology

The oscillation frequency is the inverse of the output time of a signal to process via an inverter cell. It is calculated by the estimation of rise time and fall time of the considered signal. For the oscillator triggering an initial voltage is applied to the circuit. Supply of 1 V is used at this point to generate the output to the circuit. The supply voltage is always greater to the threshold voltage Vth. Just the once, ring oscillator is triggered; it will continuously oscillated until the running point is up [22]. The applied capacitors range will affects the charging and discharging time. For this simulation, 1 pF capacitor is used. This external load capacitor is quite large to the gate capacitor (in femto-farad) for both NMOS and PMOS device. Fig. 7 shows the output response of the simulated oscillator.

Figure 7: Output waveform of 45 nm ring oscillator (VCO)

For designing of 3-stage ring oscillator, first the delay cell is designed for 45 nm CMOS technology. For delay cell: The length of PMOS and NMOS (Lp = Ln) is 45 nm. When the voltage transfer curve intersect the unity gain line, defined as Vout = Vin. The device transconductance (β), of NMOS is βn = kn (Wn/Ln) and for PMOS βp = kp (Wp/Lp). The ratio of (βn βp)is 1.083 but  βnβp=1.76 WnWp , so the ratio of nMOS to pMOS width is WnWp=1.63 . After the mathematical analysis, we get the ratio of (Wn/Ln) = 5.725 nm , Wn = 5.725*45 nm = 257.62 nm = 278 nm, But (Wp/Wn) = 1.63 nm , so Wp = 1.63* Wn = 1.63*278 nm = 419.91 nm = 420 nm. Tab. 1, defines the various parameters for ring oscillator.

The running time of ring oscillator circuit is 200 ns. In favor of initial performance validation, this time is stretched enough so that the values can be straightforwardly deliberated. Although, this step time is excessively huge so the output waveform may be abrupt or imprecise. A step time of 10 ns was used to generate smooth output waveform.

4  Simulations and Analysis of Ring Oscillator with Sweep Capacitor

The circuit diagram Fig. 8 of three-stage ring oscillator is used with the variable capacitor. The variable capacitor is used to find out the frequency analysis based on the different parameters. The circuit diagram of three variable capacitor ranges from 1 to 100 pF is shown to the figure. As by the output waveforms, it is shown that as the value of capacitor is low the circuit produces the high frequency.

Figure 8: Simulated circuit diagram using variable capacitor

The overall simulated output waveforms with variable capacitance values are shown by the following Figs. 9 to 11.

Figure 9: The O/P waveforms @1 pF to 100 pF capacitors values

Figure 10: Output responses @ 1.668 pF and @ 2.78 pF capacitor

Figure 11: Response @ 4.64 pF capacitor and @ 1 to 100 pF capacitor

5  Results and Discussion

The different parameter obtained by the frequency analysis and the output responses are presented by the Tabs. 2 and 3. The different values of capacitor will alter the values of frequency obtained. As by the result, it is clear that by increasing the capacitor value the obtained frequency is low. Therefore, both the parameters are inversely proportional. The Figs. 12 and 13 are the pictorial graphs of the relation of both the parameters.

Figure 12: Bar chart of obtained frequency and variable capacitor

Figure 13: Area diagram of time period and frequency of ring oscillator

The graph shows the relation between capacitor value and the value of frequency.

6  Conclusions and Future Work

The 5 MHz frequency band has unsurprising propagation merits that unite the paramount aspect for 40 meters and 80 meters range. This can be used to provide stable NVIS interactions throughout dusk and shadows. The operational frequency is based on the main parameters like time period and the capacitor values. In the core work, a 45 nm CMOS transistor is designed and simulated using cadence tool. The main ring oscillator is designed using 1 pF fixed capacitor and having 5.2 MHz frequency with Threshold voltage of −0.22 V and 0.22 V. The oscillations are smooth without glitch. The striking feature for this paper is taken a tradeoff among capacitor and frequency values. In this paper various performance curve for the relation of frequency and capacitor values is established. The projected ring oscillators attain the frequency range of 0.4081 to 5.2 MHz with the variable capacitance for three-stage ring oscillator. The power consumption of 1.852 μW is analyzed at 1 V supply for three-stage oscillator. This oscillator is used for CW mode radio communication, high part transmitters, clock generation, data transfer systems and recovery systems, and low power applications.

Funding Statement: The authors received no specific funding for this study.

Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the present study.

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