Robust Sensor—Less PR Controller Design for 15-PUC Multilevel Inverter Topology with Low Voltage Stress for Renewable Energy Applications

1  Introduction

Over the past decade, the rapid depletion of non-renewable energy resources has become a pressing issue due to increasing global power consumption. Power industries now face significant challenges in meeting this growing demand. Reports from the World Research Organization have highlighted how population growth and increased atmospheric pollutant emissions are intensifying environmental threats, including greenhouse effects and the accelerated melting of ice sheets. As a response, the adoption of renewable energy sources has become vital—not only for addressing environmental concerns but also for supporting energy needs in sectors like electric vehicles (EVs). Multilevel inverters (MLIs) are emerging as key technologies for achieving efficient power generation from solar, wind, and other renewables.

In modern power systems, industries are increasingly utilizing inverters for highly effective conversion across a range of applications, from low- and high-power standalone systems to grid-connected networks. However, grid integration introduces harmonic distortion, particularly under varying nonlinear loads. Conventional passive filters fall short in suppressing high-order harmonics from such loads. As a result, the advanced features of MLIs are increasingly being leveraged to mitigate these challenges and enhance the quality and efficiency of power conversion [1,2].

1.    Lower order harmonics

2.    High number of levels with low PSC

3.    Transient outputs

4.    Regulated with a lower to higher switching frequency

5.    Minor switching losses

This research paper primarily focuses on the above-mentioned features using a traditional asymmetrical MLI. Asymmetrical MLIs can control higher-order harmonics with fewer power semiconductor components (PSC) for non-linear loads. The research particularly emphasizes a modified switching control algorithm with sensorless PR control for a 15-level PUC MLI.

In recent years, multilevel inverters (MLIs) have garnered significant attention in the power and electric vehicle (EV) sectors due to their unique advantages, including reduced harmonics, lower switching losses, and improved efficiency. Conventional MLI topologies, such as the Neutral Point Clamped (NPC) by Nabae et al., Flying Capacitor (FC) by Meynard et al., and Cascaded H-Bridge (CHB) by Peng et al., each present distinct control challenges [3]. Although level-shifted and space vector PWM techniques with closed-loop controllers can partially mitigate these issues, the FC topology often faces voltage balancing difficulties related to clamping capacitors, while CHB topology struggles with complexity due to the need for phase-shifting transformers and isolated DC sources. As a result, recent research has focused on asymmetrical and advanced MLI designs to overcome these drawbacks [4,5].

Asymmetrical MLI’s are control harmonics efficiently and those topologies have more levels with lower PSC. Packed U Cell (PUC) topologies offer low switching losses, reduced harmonics, and higher voltage levels with fewer power semiconductor components, making them ideal for modern grid and EV applications. Moreover, digital twin-driven IoT architectures have further improved the capability of such systems to monitor, diagnose, and optimize performance, especially for electrified vehicle platforms [6]. Consequently, advancements in sensorless control and digital integration are enhancing the reliability and efficiency of multilevel inverter systems for next-generation power electronic applications [7,8]. This work explores a modified switching algorithm and sensorless PR controller for the 15-level PUC inverter, aiming to control load voltage and current ripples using level-shifted PWM. The compact 15-PUC inverter is adaptable for medium to high-power systems, standalone operations, and EV platforms. Fig. 1 compares the semiconductor requirements for various conventional and PUC topologies, demonstrating that the 15-PUC design significantly minimizes the need for isolating transformers and bulky components, thereby reducing system costs [9].

Figure 1: Power semiconductor components for 15-level inverters

The proposed 15-level Packed U Cell (15-PUC) inverter features a simplified architecture, utilizing only 11 components, 8 IGBT switches and 3 sources or capacitors unlike more complex conventional multilevel inverter designs. In this study, the 15-PUC inverter is operated using a level-shift pulse width modulation (PWM) technique alongside a sensorless proportional-resonant (PR) controller. The PR controller is shown, through stability analysis, to effectively suppress higher-order harmonics even at lower switching frequencies. Additionally, the 15-PUC is managed by a novel switching algorithm that further enhances performance and reliability.

Traditionally, researchers have managed PUC and other conventional multilevel inverter topologies using controllers such as PI, hysteresis, and various optimized strategies [10–12]. However, PI controllers exhibit significant drawbacks in DC-AC applications, including sluggish response to system disturbances, pronounced overshoot at startup, and sensitivity-dependent gain issues [13–16]. Hysteresis controllers, while simple to implement for MLIs, struggle to maintain constant amplitude and switching frequency, often resulting in bandwidth and tolerance errors [17,18]. Other linear and optimized controllers frequently encounter challenges such as capacitor voltage imbalance, zero and third-order harmonics, and persistent static and dynamic errors. To address these shortcomings, this paper proposes a simple and efficient sensorless PR controller for the 15-level PUC inverter [19,20]. The PR controller automatically balances capacitor voltages without relying on voltage or feedback sensors [21,22]. Fig. 2 illustrates the modulation methods employed for various MLI topologies, highlighting the use of different controllers to optimize renewable energy system performance. Furthermore, harmonic elimination approaches for MLIs are discussed in the context of advanced control techniques [23].

Figure 2: Modulation methods for MLI topologies

Accordingly, the structure of this paper is as follows: Section 2 details the novel switching algorithm and modeling of the 15-PUC multilevel inverter topology. Section 3 presents the advanced level-shift multicarrier-based SPWM approach. Section 4 introduces the sensorless PR voltage controller, integrated within both the PWM method and switching algorithm. Section 5 provides simulation results and performance comparison of the 15-PUC inverter. Section 6 concludes the paper and provides references, respectively.

2  Novel Switching Algorithm For 15-PUC MLI

In conventional switching sequence, power switches are unable to trigger simultaneously, and all switches are triggered in mode 8. (2–3) & (13–14) modes are quite opposite compared to novel switching. Following Table 1 represents the switching algorithm for 15-PUC MLI and it’s developed through 8 power semiconductor switches (S1,S3,S5,S7,S2,S4,S6,S8) only. Through, 15 level MLI switching arrangement consist of 4 switches (S1,S3,S5,S7) which it acts as normal mode of operation and another four power switches (S2,S4,S6,S8) are acting as complimentary mode operations. It is required to operate 15 operating modes, for above zero level is positive half cycle and considers seven operating voltage modes and below zero level is negative half cycle considering as another seven operating voltage modes. Moreover, positive switching modes and negative modes are operate equally, based on this we balase the capacitors also automatically. So 15PUC not required to do other balancing mechanisms. The voltage levels are defined by the following equation.

V1=230Vdc,V2=99Vdc,V3=33Vdc(1)

The formula defines three distinct DC voltage levels used in a multilevel inverter system: V1=230V,V2=99V,V3=33V, which are strategically selected to generate multiple output voltage steps. These levels enable the inverter to synthesize a high-quality AC waveform with reduced harmonic distortion and improved efficiency by combining different voltage sources. The variation in voltage magnitudes allows for finer control over the output waveform, making the system suitable for applications requiring precise voltage regulation and enhanced power quality.

15-PUC MLI is represented in Fig. 3. By using the novel switching algorithm, the mode of operation with current flow direction is presented in Table 1.

Figure 3: Single-phase 15-PUC MLI

2.1 Voltage Stress & TSV

The maximum voltage stress across the switches is important criteria for the MLI’s, this can be called as total standing voltage (TSV). It is equal to the maximum voltage across the switches. The Fig. 4 represents the voltage stress on switches S1,S3,S5,S7 has been analyzed for per cycle of operation and complementary operation is applied for the switches S2,S4,S6,S8, respectively.

Figure 4: Voltage stress on semiconductor switches for 15-PUC MLI

The ratio of normalized voltage stress NVstrs is denoted by actual voltage stress Vstrs across switch with maximum voltage VLmax. This paper explains the voltage stress at each switch and normalized voltage stress shown in Table 2. Fig. 5 shows that the stress distribution of each switch has been presented.

VLmax=(Nlev−1)2(2)

NVstrs=VstrsVLmax(3)

Figure 5: Voltage stress distribution of each switch

The TSV plays an major role in finding the cost function and efficiency of MLI. Its consists of all MBV values for the overall semiconductor devices in topology. In 15-PUC topology all switches are un-directional and one-leg is operating in complementary. Therefore, the TSV is determined using the following equation:

TSV=2(VS1+VS3+VS5+VS7)=2(2Vdc+7Vdc+5Vdc+Vdc)=30Vdc(4)

Hence the TSV is found to be 30Vdc, and the TSVpu is determined using the below equation:

TSVpu=TSVVLmax(5)

TSVpu=30Vdc7Vdc(6)

TSVpu=4Vdc(7)

2.2 Cost Function Calculation

The cost function (CF) analysis has been presented in this section for 15-PUC MLI topology. Many parameters are to be considered like no of switches Nsw, no of diodes Nd, no of capacitors Nc, no of voltage sources Nvs, no of driver circuits Ndc and TSVpu with the below equation:

CF=Nsw+Nd+Nc+Nvs+Ndc+αTSVpu(8)

In general, α to be considered either it should be lesser than 1 or greater than 1. Here authors considered 0.5 and 1.5 as the values of α for the optimal analysis. In the 15-PUC there are no diodes and capacitors hence it is neglected from the calculations. Further the component per level is to be determined using the equation

CF/Nlev=(Nsw+Nd+Nc+Nvs+Ndc+αTSVpu)Nlev(9)

From the Table 3, the detailed analysis of CF for various MLI’s has been discussed with latest topologies and some conventional topologies.

The detailed comparisons of various MLS’s has been presented in Figs. 6–12 in terms of no of switches, voltage sources, diodes, capacitors, TSVpu, THD% and CF/Nlev, respectively.

Figure 6: No of switches Nsw between PUC and recent MLI’s [23–34]

Figure 7: No of voltage sources Nvs between PUC and recent MLI’s [23–34]

Figure 8: No of diodes Nd between PUC and recent MLI’s [25,26,29,31]

Figure 9: No of capacitors Nc between PUC and recent MLI’s [25]

Figure 10: TSVpu between PUC and recent MLI’s [31,33,34]

Figure 11: THD% between PUC and recent MLI’s [23,25,26,28–34]

Figure 12: CF/Nlev between PUC and recent MLI’s [31,33,34]

3  Advanced Level Shift Multi-Carrier Based SPWM Technique

Multilevel inverters (MLIs) can be regulated using a variety of open- and closed-loop strategies, many of which present considerable design and implementation complexities. Carrier-based sinusoidal pulse width modulation (SPWM) techniques, however, provide an efficient and cost-effective approach to controlling MLI output voltage and minimizing harmonic distortion. This study focuses on controlling the 15-level Packed U Cell (15-PUC) inverter at lower switching frequencies through advanced carrier-based modulation schemes. Specifically, it introduces an advanced level-shift triangular multi-carrier phase disposition SPWM (PD-SPWM) method, operating at a 3 kHz switching frequency. The level-shift PD-PWM approach demonstrates superior performance compared to other level-shift PWM techniques, under both constant and variable frequency operations [24,25].

In the phase disposition SPWM (PD-SPWM) approach, all 14 carrier signals are configured with identical amplitude and are precisely aligned such that each maintains a 0° phase shift relative to the others, as illustrated in Fig. 13. Throughout the duration from 0 to 0.001 s, a single triangular carrier waveform is employed. The reference sinusoidal waveform intersects each of the 14 carriers at distinct points, thereby producing unique switching pulses for the eight semiconductor switches in the inverter.

Figure 13: Advanced multi-carrier based conventional level shift PD-SPWM

The selection of multi carriers are depends on number of output voltage levels, 15-PUC MLI requires 14 carriers pulses (Nca number of multi carriers = −1 + number of output levels).

NCa=NL−1(10)

where, NCa = number of carriers & NL = Number of levels

The variation of MLI output voltage and levels are depends on modulation index MI.

MIinv=AmNC∗Ac(11)

where, Am is the amplitude of reference modulation signal and Ac is amplitude of carrier signal. The advance level shift PWM is arranged by 14 carriers only, each carrier is travelling with 3 kHZ switching frequency fr and reference wave fs is travelling 50 Hz frequency. While switching pulses are generated by comparing on these modulation signals. The frequency of modulation ratio is expressed by below.

Mfinv=fsfr(12)

Following Fig. 14 consists of a half quarter predetermined switching angle voltage stepped waveform. The stepped waveform consists of both even and odd harmonics, but even harmonics are not considerable to effect the system. The advanced level shift PWM is eliminate zero and third order harmonics, we consider to control odd order harmonics only.

Figure 14: 15 level steeped waveform with half quarter switch angles

The Fourier series representation of the 15-level fundamental stepped voltage waveform is expressed as follows.

The novel switching algorithm is influence to 15-PUC outputs predictively. Through that comparison of sin & carrier waveforms, required unique switching pulses of 15-PUC MLI is shown in Fig. 15. Blue colour switching pulses S1,S5,S3,S7 are act as normal operation switches and red colour switching pulses S2,S6,S4,S8 are act as complementary operation switches.

Figure 15: Required switching pulses of 15-PUC MLI peak voltage Vp = 230 V

Every half cycle consists of 15 time periods only Tp=10ms(T=0.01). Every pulse width, one time period T1p = T15=0.0006666 (Pulse-pulse 0.0006666 ms). Every half cycle consists of 15 multi different firing angles θa = 180∘, each pulse width firing angle is θ1a = 180∘15=12∘.

Following Table 4 consists of voltage increment and decrement angles for half quarter cycle.

4  Sensor-Less PR Voltage Controller Integrated into PWM & Switching Algorithm

15-level PWM contains, sinusoidal reference waveform with fourteen carriers is already discussed in above. The sin reference (Vsin⁡_ref) travels vertically towards fourteen carriers (Cr1 to Cr14). More overly, unique switching pulses are built up by a novel switching algorithm consisting of one to fifteen switching modes. The (Vsin⁡_ref) is positive, one to 8 switching modes are activated periodically, and output voltage levels are positive. Also, (Vsin⁡_ref) is negative, nine to fifteen switching modes are activated periodically, and output voltage levels have become negative.

According to previous research, conventional linear controllers encounter significant challenges in accurately sensing and responding to abrupt changes in load and source parameters, as well as in maintaining stable capacitor voltages. To overcome these limitations, this work introduces a sensorless Proportional Resonant (PR) controller specifically designed for the 15-level Packed U Cell (15-PUC) multilevel inverter. Fig. 16 provides a schematic representation of the sensorless voltage controller integrated within the 15-PUC system.

Figure 16: Sensor less controller for 15-PUC systems

The sensorless PR controller for the inverter system regulates the output voltage without relying on physical sensors. It utilizes a combination of a Proportional Resonant (PR) controller, a Phase-Locked Loop (PLL), and a PWM-based switching algorithm. The PR controller receives the reference voltage Vref and compares it with the actual output to generate an error signal. This error is processed using the PR control law, which is specifically designed to eliminate steady-state error for sinusoidal signals. The transfer function of the PR controller is given by:

GPR(S)=Kp+Ki∗SS2+W02

where Kp is the proportional gain, Ki is the resonant gain, and ω0 = 2πf0 is the resonant frequency corresponding to the grid or desired output frequency. This structure enables the controller to provide high gain at the resonant frequency, ensuring accurate tracking of sinusoidal references. The PLL (Phase-Locked Loop) ensures synchronization with the grid or reference signal, while the PWM (Pulse Width Modulation) algorithm converts the control signal into switching pulses for the inverter switches (S1 to S8). Together, these components facilitate precise voltage control and waveform shaping, even in the absence of direct current or voltage sensors—making the system more robust and cost-effective for practical applications.

The PR controller is designed to track sinusoidal reference signals with zero steady-state error, making it ideal for AC systems like inverters. Unlike a traditional PI controller, which struggles with AC signals, the PR controller introduces a resonant term that provides infinite gain at a specific frequency (usually the grid frequency). The PR controller predominantly controls the amplitude, described phase shifting signals are fetched from load. Measured voltage angle from the grid is injected PLL block for extracting the angle. PLL block supports to control switching & grid frequencies, and it provides proper phase shift with the help of sin block combination. The maximum value of reference current im∗ is also multiplied with sin block for better controlling the system power. From Fig. 16, the reference current is sin block output is∗ compared, and results are injected towards the PI controller by eliminating the steady-state error. After that, the conventional PWM block collects the signal from PI for standalone systems. This sensor-less system is controlled DC link capacitor voltage constantly, depending on switching frequency and 5% ripple voltage. These controllers provide zero steady state error, lower harmonics, and develop exact phase shift angle with nominal operating frequency [26,27].

5  Simulation Results

The 15-PUC is realized in MATLAB/Simulink environment for the proposed PR controller. The controller balances the capacitor voltages automatically, and the performance is evaluated for standalone applications. The Load parameters of 15-PUC MLI are presented in Table 5.

Fig. 17a,b represents the 15 level load voltage and load current output waveforms of 15-PUC MLI for R load. By using advanced sensor less PR controller the load voltage & current harmonic Figures represent at Fig. 17c,d (9.48% & 3.87%), by which it eliminates the bulky harmonic design of filter circuits. The Fast Fourier Transform (FFT) analysis proves that load current THD is falling under universal IEEE standard 519.

Figure 17: (a–d) Output waveforms for 15-PUC MLI using standalone mode for R load

The load values of RL are R1 & L1: 40 Ω & 300 mH, respectively. Fig. 18a,b represents the 15-level load voltage and load current output waveforms of 15-PUC MLI. By using advanced sensor less PR controller the load voltage & current harmonics are found to be less than 5% (i.e., 3.70% & 1.09%) by which it eliminates zero and third order harmonics effectively. The voltage current harmonics are represented at Fig. 18c,d. The Fast Fourier Transform (FFT) analysis proves that THD is falling under universal IEEE standard 519.

Figure 18: (a–d) Output waveforms for 15-PUC MLI using standalone mode for RL load

The performance of the 15-level PUC MLI is evaluated under varying source regulations within the interval of 0 to 0.04 ms, with a step change in load conditions illustrated in Fig. 19. The results indicate that the voltage and current waveforms achieve stabilization at approximately 0.05 ms, with a settling time of just 0.01 ms. For this analysis, resistive and inductive load values are set at 40, 100 Ω, and 300, 200 mH, respectively. The highlighted sections in the figures provide detailed views of the inverter’s dynamic response under different loading scenarios.

Figure 19: Step change in input voltage

Figs. 19 and 20 further demonstrate the electrical system’s behavior following a sudden increase in input voltage—from 200 V to 230 V at around 0.045 s, as shown in Fig. 19. The corresponding output voltage initially exhibits transient oscillations, eventually stabilizing into a steady sinusoidal waveform between −250 V and +250 V. This dynamic-to-steady-state transition showcases the robust response and stability of the system. Fig. 20a clearly depicts the output response, effectively capturing both transient phases (emphasized by the dotted oval) and the subsequent sustained sinusoidal operation. This ability to quickly recover and maintain regular oscillation after a disturbance is a strong indicator of robust system design and reliable performance in electrical engineering applications.

Figure 20: (a,b) Dynamic behavior of 15-PUC MLI

Fig. 20b presents the alternating current (AC) waveform over a time interval of 0 to 0.2 s. The red sinusoidal trace smoothly oscillates between −1 and +1 units, demonstrating a stable and symmetric AC signal. This regular and distortion-free pattern is characteristic of properly functioning electrical systems and highlights the inherent periodicity of AC current flow. The observed consistency in amplitude and symmetry indicates that the system operates without transient disruptions, serving as an exemplary depiction of ideal AC current behavior in practical electrical circuits.

Experimental: The practical implementation of the proposed sensorless controller for the 15-level Packed U-Cell (PUC) inverter system presents several challenges. First, achieving accurate current and voltage control without physical sensors demands highly reliable estimation algorithms, which can be sensitive to noise, temperature variations, and component tolerances. Second, the integration of advanced control blocks like the PR controller and Phase-Locked Loop (PLL) requires precise tuning to maintain synchronization and stability, especially under dynamic load conditions. Third, the real-time execution of the switching algorithm and PWM generation necessitates high-speed digital signal processing hardware, which can increase system complexity and cost. Additionally, ensuring consistent capacitor voltage balancing and managing switching losses across multiple levels further complicates the design and implementation process. We can close this gap in the future.

6  Conclusion

In this work, a sensorless PR controller-based 15-level Packed U Cell (15-PUC) multilevel inverter has been developed and realized. A novel switching algorithm was designed and implemented to optimize the inverter operation. The proposed PR controller integrated with an advanced level-shift PD-PWM technique effectively reduces switching stress while enhancing transient response. This controller actively compensates for DC-link capacitor voltage without needing feedback from the source or load, thereby eliminating the requirement for voltage sensors. Simulation results for resistive (R) and resistive-inductive (RL) load cases demonstrate that the total harmonic distortion (THD) remains within the IEEE-519 standard limits. The proposed approach also shows robust performance under dynamic load changes, with DC voltage variations from 200 V to 230 V. Overall, the 15-PUC inverter topology combined with the sensorless PR controller is highly suitable for renewable energy and grid-connected applications.

Acknowledgement: Authors used Perplexity AI for English language polishing.

Funding Statement: The authors received no specific funding for this study.

Author Contributions: Conceptualization, K. Naga Venkata Siva, Damodhar Reddy, and P. Krishna Murthy; methodology, Kiran Kumar Pulamolu, M. Dharani, and T. Venkatakrishnamoorthy; validation, K. Naga Venkata Siva, Damodhar Reddy, and P. Krishna Murthy; formal analysis, Kiran Kumar Pulamolu, M. Dharani, and T. Venkatakrishnamoorthy; investigation M. Dharani, and T. Venkatakrishnamoorthy; Writing—original draft, Kiran Kumar Pulamolu, Damodhar Reddy, and P. Krishna Murthy; Writing—review & editing, K. Naga Venkata Siva; supervision, T. Venkatakrishnamoorthy. All authors reviewed the results and approved the final version of the manuscript.

Availability of Data and Materials: Not applicable.

Ethics Approval: Not applicable.

Conflicts of Interest: The authors declare no conflicts of interest to report regarding the present study.

Nomenclature

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