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IC Pattern Based Power Factor Maximization Model for Improved Power Stabilization

N. Hariharan1,*, Y. Sukhi2, N. Kalaiarasi1

1 R.M.K. College of Engineering and Technology, Thiruvallur, 601206, India
2 R.M.K. Engineering College, Thiruvallur, 601206, India

* Corresponding Author: N. Hariharan. Email: email

Intelligent Automation & Soft Computing 2023, 36(1), 401-414. https://doi.org/10.32604/iasc.2023.030768

Abstract

The voltage fluctuation in electric circuits has been identified as key issue in different electric systems. As the usage of electricity growing in rapid way, there exist higher fluctuations in power flow. To maintain the flow or stability of power in any electric circuit, there are many circuit models are discussed in literature. However, they suffer to maintain the output voltage and not capable of maintaining power stability. To improve the performance in power stabilization, an efficient IC pattern based power factor maximization model (ICPFMM) in this article. The model is focused on improving the power stability with the use of IC (Inductor and Conductor) towards identifying most efficient circuit for the current duty cycle according to the input voltage, voltage in capacitor and output voltage required. The model with boost converter diverts the incoming voltage through number of conductors and inductors. By triggering specific inductor, a specific capacitor gets charged and a particular circuit gets on. The model maintains number of IC (Inductor and Conductor) patterns through which the power flow occurs. According to that, the pattern available, the mofset controls the level of power to be regulated through any circuit. From the pattern, the model computes the Circuits Switching Loss and Circuits Conduction Loss for various circuits. According to the input voltage, the model estimates Circuit Power Stabilization Support (CPSS) according to the voltage available in any capacitor and input voltage. Using the value of CPSS, the model trigger optimal number of circuits to maintain voltage stability. In this approach, more than one circuit has been triggered to maintain output voltage and to get charged. The proposed model not only maintains power stability but also reduces the wastage in voltage which is not utilized. The proposed model improves the performance in voltage stability with less switching loss.

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Cite This Article

APA Style
Hariharan, N., Sukhi, Y., Kalaiarasi, N. (2023). IC pattern based power factor maximization model for improved power stabilization. Intelligent Automation & Soft Computing, 36(1), 401-414. https://doi.org/10.32604/iasc.2023.030768
Vancouver Style
Hariharan N, Sukhi Y, Kalaiarasi N. IC pattern based power factor maximization model for improved power stabilization. Intell Automat Soft Comput . 2023;36(1):401-414 https://doi.org/10.32604/iasc.2023.030768
IEEE Style
N. Hariharan, Y. Sukhi, and N. Kalaiarasi "IC Pattern Based Power Factor Maximization Model for Improved Power Stabilization," Intell. Automat. Soft Comput. , vol. 36, no. 1, pp. 401-414. 2023. https://doi.org/10.32604/iasc.2023.030768



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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