Jiangang Lu, Ruifeng Zhao^*, Zhiwen Yu, Yue Dai, Kaiwen Zeng

CMC-Computers, Materials & Continua, Vol.78, No.3, pp. 4453-4469, 2024, DOI:10.32604/cmc.2024.048020

Abstract Time synchronization (TS) is crucial for ensuring the secure and reliable functioning of the distribution power Internet of Things (IoT). Multi-clock source time synchronization (MTS) has significant advantages of high reliability and accuracy but still faces challenges such as optimization of the multi-clock source selection and the clock source weight calculation at different timescales, and the coupling of synchronization latency jitter and pulse phase difference. In this paper, the multi-timescale MTS model is conducted, and the reinforcement learning (RL) and analytic hierarchy process (AHP)-based multi-timescale MTS algorithm is designed to improve the weighted summation of synchronization latency jitter standard deviation… More >

Jeongha Lee¹, Hyokyung Bahn^2,*

CMC-Computers, Materials & Continua, Vol.76, No.1, pp. 607-629, 2023, DOI:10.32604/cmc.2023.039236

Abstract Due to the recent trend of software intelligence in the Fourth Industrial Revolution, deep learning has become a mainstream workload for modern computer systems. Since the data size of deep learning increasingly grows, managing the limited memory capacity efficiently for deep learning workloads becomes important. In this paper, we analyze memory accesses in deep learning workloads and find out some unique characteristics differentiated from traditional workloads. First, when comparing instruction and data accesses, data access accounts for 96%–99% of total memory accesses in deep learning workloads, which is quite different from traditional workloads. Second, when comparing read and write accesses,… More >

Rajkumar Sarma¹, Cherry Bhargava², Ketan Kotecha^3,*

CMC-Computers, Materials & Continua, Vol.72, No.1, pp. 481-495, 2022, DOI:10.32604/cmc.2022.024516

Abstract In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further… More >

G. Prathiba^1,*, M. Santhi²

Intelligent Automation & Soft Computing, Vol.31, No.3, pp. 1611-1626, 2022, DOI:10.32604/iasc.2022.018975

Abstract High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the… More >