Arpit Jain¹, Rakesh Kumar Dwivedi¹, Hammam Alshazly^2,*, Adesh Kumar³, Sami Bourouis⁴, Manjit Kaur⁵

CMC-Computers, Materials & Continua, Vol.71, No.2, pp. 4085-4100, 2022, DOI:10.32604/cmc.2022.023017

Abstract The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher… More >

Namit Gupta^1,*, Kunwar Singh Vaisla², Arpit Jain³, Adesh Kumar⁴, Rajeev Kumar³

Computer Systems Science and Engineering, Vol.40, No.3, pp. 1073-1084, 2022, DOI:10.32604/csse.2022.019911

Abstract Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip… More >