T. G. Sargunam^1,2,*, Lim Way Soong¹, C. M. R. Prabhu¹, Ajay Kumar Singh³

CMC-Computers, Materials & Continua, Vol.72, No.2, pp. 3425-3446, 2022, DOI:10.32604/cmc.2022.023452

Abstract The use of Internet of Things (IoT) applications become dominant in many systems. Its on-chip data processing and computations are also increasing consistently. The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications. The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system. Therefore, a process tolerant SRAM cell with low power, improved delay and better stability is presented in this research paper. The proposed cell comprises 11 transistors designed with symmetric… More >

S. Rooban¹, Moru Leela¹, Md. Zia Ur Rahman^1,*, N. Subbulakshmi², R. Manimegalai³

CMC-Computers, Materials & Continua, Vol.72, No.1, pp. 1309-1321, 2022, DOI:10.32604/cmc.2022.023934

Abstract Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energy-consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without… More >