Allam Abumwais1,*, Adil Amirjanov1, Kaan Uyar1, Mujahed Eleyat2
CMC-Computers, Materials & Continua, Vol.70, No.3, pp. 4583-4597, 2022, DOI:10.32604/cmc.2022.020529
Abstract Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown… More >
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