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Dual-Port Content Addressable Memory for Cache Memory Applications

Allam Abumwais1,*, Adil Amirjanov1, Kaan Uyar1, Mujahed Eleyat2

1 Department of Computer Engineering, Near East University, Nicosia, N. Cyprus via Mersin-10, Turkey
2 Computer Systems Engineering, Arab American University, Jenin, 240, Palestine

* Corresponding Author: Allam Abumwais. Email: email

(This article belongs to this Special Issue: Application of Big Data Analytics in the Management of Business)

Computers, Materials & Continua 2022, 70(3), 4583-4597.


Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.


Cite This Article

A. Abumwais, A. Amirjanov, K. Uyar and M. Eleyat, "Dual-port content addressable memory for cache memory applications," Computers, Materials & Continua, vol. 70, no.3, pp. 4583–4597, 2022.

cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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