Allam Abumwais^*, Mujahed Eleyat

CMC-Computers, Materials & Continua, Vol.77, No.1, pp. 615-632, 2023, DOI:10.32604/cmc.2023.038810

Abstract Recent architectures of multi-core systems may have a relatively large number of cores that typically ranges from tens to hundreds; therefore called many-core systems. Such systems require an efficient interconnection network that tries to address two major problems. First, the overhead of power and area cost and its effect on scalability. Second, high access latency is caused by multiple cores’ simultaneous accesses of the same shared module. This paper presents an interconnection scheme called N-conjugate Shuffle Clusters (NCSC) based on multi-core multi-cluster architecture to reduce the overhead of the just mentioned problems. NCSC eliminated the need for router devices and… More >

Allam Abumwais^*, Mahmoud Obaid

CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 4951-4963, 2023, DOI:10.32604/cmc.2023.032822

Abstract Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used… More >

Allam Abumwais^1,*, Adil Amirjanov¹, Kaan Uyar¹, Mujahed Eleyat²

CMC-Computers, Materials & Continua, Vol.70, No.3, pp. 4583-4597, 2022, DOI:10.32604/cmc.2022.020529

Abstract Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown… More >

R. Mythili^{1, *}, P. Kalpana²

CMC-Computers, Materials & Continua, Vol.62, No.3, pp. 1097-1107, 2020, DOI:10.32604/cmc.2020.08396

Abstract NIDS (Network Intrusion Detection Systems) plays a vital role in security threats to computers and networks. With the onset of gigabit networks, hardware-based Intrusion Detection System gains popularity because of its high performance when compared to the software-based NIDS. The software-based system limits parallel execution, which in turn confines the performance of a modern network. This paper presents a signature-based lookup technique using reconfigurable hardware. Content Addressable Memory (CAM) is used as a lookup table architecture to improve the speed instead of search algorithms. To minimize the power and to increase the speed, precomputation based CAM (PBCAM) can be used,… More >