Allam Abumwais^*, Mahmoud Obaid

CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 4951-4963, 2023, DOI:10.32604/cmc.2023.032822

Abstract Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used… More >

Allam Abumwais^1,*, Adil Amirjanov¹, Kaan Uyar¹, Mujahed Eleyat²

CMC-Computers, Materials & Continua, Vol.70, No.3, pp. 4583-4597, 2022, DOI:10.32604/cmc.2022.020529

Abstract Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown… More >