Deshun Li¹, Shaorong Sun², Qisen Wu², Shuhua Weng¹, Yuyin Tan², Jiangyuan Yao^1,*, Xiangdang Huang¹, Xingcan Cao³

Computer Systems Science and Engineering, Vol.46, No.1, pp. 433-443, 2023, DOI:10.32604/csse.2023.034368

Abstract As a critical infrastructure of cloud computing, data center networks (DCNs) directly determine the service performance of data centers, which provide computing services for various applications such as big data processing and artificial intelligence. However, current architectures of data center networks suffer from a long routing path and a low fault tolerance between source and destination servers, which is hard to satisfy the requirements of high-performance data center networks. Based on dual-port servers and Clos network structure, this paper proposed a novel architecture to construct high-performance data center networks. Logically, the proposed architecture is constructed by inserting a dual-port server… More >

Allam Abumwais^1,*, Adil Amirjanov¹, Kaan Uyar¹, Mujahed Eleyat²

CMC-Computers, Materials & Continua, Vol.70, No.3, pp. 4583-4597, 2022, DOI:10.32604/cmc.2022.020529

Abstract Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown… More >

Surajo Muhammad^1,*, Jun Jiat Tiang¹, Sew Kin Wong¹, Jamel Nebhen², Amjad Iqbal¹

CMC-Computers, Materials & Continua, Vol.69, No.1, pp. 487-501, 2021, DOI:10.32604/cmc.2021.018292

Abstract This paper proposed the design of a dual-port rectifier with multi-frequency operations. The RF rectifier is achieved using a combination of L-section inductive impedance matching network (IMN) at Port-1 with a multiple stubs impedance transformer at Port-2. The fabricated prototype can harvest RF signal from GSM/900, GSM/1800, UMTS/2100, Wi-Fi/2.45 and LTE/2600 frequency bands at (0.94, 1.80, 2.10, 2.46, and 2.63 GHz), respectively. The rectifier occupies a small portion of a PCB board at 0.20 λg × 0.15 λg. The proposed circuit realized a measured peak RF-to-dc (radio frequency direct current) power conversion efficiency (PCE) of (21%, 22.76%, 25.33%, 21.57%, and… More >

Surajo Muhammad^1,*, Jun Jiat Tiang¹, Sew Kin Wong¹, Amjad Iqbal¹, Amor Smida², Mohamed Karim Azizi³

CMC-Computers, Materials & Continua, Vol.68, No.1, pp. 167-184, 2021, DOI:10.32604/cmc.2021.016133

Abstract This paper presents a compact multi-band rectifier with an improved impedance matching bandwidth. It uses a combination of п–matching network (MN) at Port-1, with a parallel connection of three cell branch MN at Port-2. The proposed impedance matching network (IMN) is adopted to reduce circuit complexity, to improve circuit performance, and power conversion efficiency (PCE) of the rectifier at low input power. The fabricated rectifier prototype operates at 0.92, 1.82, 2.1, 2.46 and 2.65 GHz covering GSM/900, GSM/1800, UMTS2100, and Wi-Fi/2.45–LTE2600. The size of the compact rectifier on the PCB board is 0.13λ_g × 0.1λ_g. The fabricated rectifier achieved an… More >